Simulate the operation of the circuit shown in Fig. 30.59 (a cascade of Figs. 30.55 and 30.56). Comment on the ideal outputs and the simulation results.
This circuit shows the same mismatched capacitors in the multiply-by-two stage as we saw in Ex. 30.18. The averaging stage also shows mismatched capacitors with arbitrary values. Again, as in Ex. 30.18, the ideal output voltage is 1.0 V (\nu_{out+} = 1 V and \nu_{out-} = 0 V). The simulation results are shown in Fig. 30.60. The error has dropped from 5 mV to – 67 μV. It may be instructive to resimulate the capacitor error averaging topology of Fig. 30.59 using different values of capacitors in order to get a feeling for just how forgiving the topology is to mismatches.
Note that in the simulation netlist, where we are using near ideal op-amps with open loop gains of 100 million, we added switches in series with the C_I capacitors in the averaging circuit to avoid the situation of the op-amp operating open-loop with its outputs going to millions of volts when both \phi _a and \phi _h are low. (The op-amp operates open loop when \phi _s is high, which is usually not a problem in a practical circuit).