Question 30.7: Simulate the operation of the data converter S/H building bl......
Simulate the operation of the data converter S/H building block shown in Fig. 30.30. Assume C_I = C_F = 1 pF and f_s = 100 MHz.
The simulation results are shown in Fig. 30.33. In part (a) the clock signals are shown. Unlike the clock signals shown in Fig. 30.30 where the falling edge of \phi _2 is delayed from \phi _1, the simulation sets the signals so they go low at the same time. This was to avoid the outputs of the op-amp changing to very large values for the small amount of time the op-amp operates open-loop with an input signal applied.
In part (b) we show the op-amp outputs. Note how, when \phi _1 goes high, both outputs are set to the common-mode voltage by forcing the op-amp into a follower configuration (which may lead us to use switches to short the terminals of the op-amp to V_{CM} when \phi _1 is high if offset isn’t important). When \phi _3 goes high, the circuit behaves as an S/H with a gain of two. Part (c) of the figure shows the outputs connected through \phi _3 switches, as seen in Fig. 30.30, driving 10 pF load capacitances.
