Question 30.1: Suppose a 10-bit, voltage-mode DAC with the topology seen in......
Suppose a 10-bit, voltage-mode DAC with the topology seen in Fig. 30.14 is implemented where R=10k\ \text{and}\ C_L=10\ pF. Estimate the maximum clocking frequency that can be used to clock the register supplying the input words to the DAC. Verify your answer using SPICE.
For complete settling the DAC must be 10-bit accurate to within 0.5 LSBs over its full-scale range
\mathrm{Accuracy}={\frac{0.5\;L S B}{\mathrm{Full\;scale\;Tange\;(}V D D)}}={\frac{V D D/2^{N+1}}{V D D}}={\frac{1}{2^{11}}}=0.04883\%The time constant associated with the DAC and capacitive load is
R C_{L}=10k\cdot10p=100\,n sThis time constant can be related to the final ideal output voltage, V_{outfinal}, and the actual output voltage, V_{out}, using
V_{o u t}=V_{o u t f i n a l}(1-e^{-t/R C_{L}})or, relating this to the required accuracy,
\frac{1}{2^{N+1}}=1-\frac{V_{o u t}}{V_{o u t f i n a l}}=e^{-t_{set tl i n g}/R C_{L}}The required settling time is then
t_{s e t t li n g}=R C_{L}\cdot\ln2^{N+1} (30.18)
Using the numbers from this example results in t_{s e t t li n g}=762\ ns. The SPICE simulation results are shown in Fig. 30.15. The maximum clock frequency is then estimated as
f_{c l k,\mathrm{max}}={\frac{1}{t_{s e t t li n g}}}={\frac{1}{R C_{L}\cdot\ln{2^{N+1}}}} (30.19)
For this example, f_{c l k,\mathrm{max}}=1.3\ \text{MHz}. Note that the fundamental way to decrease the settling time is to decrease the resistance in the R-2R ladder (assuming we have no control over the load capacitance). The practical problem then becomes implementing the switches (MOSFETs) with a resistance small compared to R.
