Question 7.SP.23: The input admittance to a triode modeled by the small-signal......

The input admittance to a triode modeled by the small-signal equivalent circuit of Fig. 7-9(b) is obviously zero; however, there are interelectrode capacitances that must be considered for high-frequency operation.    Add these interelectrode capacitances (grid-cathode capacitance C_{gk}; plate-grid, C_{pg}; and plate-cathode, C_{pk}) to the small-signal equivalent circuit of Fig. 7-9(b).   Then   (a) find the input admittance Y_{in},   (b) find the output admittance Y_o, and   (c) develop a high-frequency model for the triode.

7.9
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(a) With the interelectrode capacitances in position, the small-signal equivalent circuit is given by Fig. 7-24.
The input admittance is
Y_{\mathrm{in}} = {\frac{I_{S}}{V_{S}}} = {\frac{I_{1}  +  I_{2}}{V_{S}}}                   (1)

But              I_{1} = {\frac{V_{S}}{1/s C_{g k}}} = s C_{g k}V_{S}               (2)

and             I_{2} = {\frac{V_{S}  –  V_{o}}{1/s C_{p g}}} = s C_{p g}(V_{S}  –  V_{o})                      (3)

Substituting (2) and (3) into (1) and rearranging give
Y_{in} = s\left[C_{g k} + \left(1  –  {\frac{V_{o}}{V_{S}}}\right)C_{p g}\right]            (4)

Now, from the result of Problem 7.21,
{\frac{V_{o}}{V_{S}}} = -{\frac{\mu R_{L}}{R_{L}  +  r_{p}}}               (5)

so (4) becomes
Y_{in} = s\left[C_{g k} + \left(1 + {\frac{\mu R_{L}}{R_{L}  +  r_{p}}}\right)C_{p g}\right]            (6)

(b) The output admittance is
Y_{o} = -{\frac{I_{L}}{V_{o}}} = -{\frac{I_{2}  –  I_{p}  –  I_{pk}}{V_{o}}}                 (7)

and                   I_{p k} = s C_{p k}V_{o}                   (8)

Let Y_{o}^{\prime} be the output admittance that would exist if the capacitances were negligible; then
I_{p} = Y_{o}^{\prime}V_{o}                   (9)

so that              Y_{o} = s\biggl[\biggl(1  +  {\frac{R_{L}  +  r_{p}}{\mu R_{L}}}\biggr)C_{p g}  +  C_{p k}\biggr]  +  Y_{o}^{\prime}                  (10)

(c) From (6) and (10) we see that high-frequency triode operation can be modeled by Fig. 7-9(b) with a capacitor C_{in} = C_{gk} + [1 + R_L/(R_L + r_p)]C_{pg} connected from the grid to the cathode, and a capacitor C_o = [1 + (R_L + r_p) = \mu R_L]C_{pg} + C_{pk} connected from the plate to the cathode.

7.24

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