Holooly Plus Logo
Holooly Plus Logo

Question 25.SG.Q.12: The logic function implemented by the circuit shown in the f......

The logic function implemented by the circuit shown in the following figure is (ground implies a logic `0’)

(a) F = AND (P, Q)              (b) F = OR (P, Q)

(c) F = XNOR (P, Q)           (d) F = XOR (P, Q)

1079457-25.12
Step-by-Step
The 'Blue Check Mark' means that this solution was answered by an expert.
Learn more on how do we answer questions.
Report Answer

I_1 and I_2 are tied to logic `1’ state. I_0 and I_3 are tied to logic `0’ state. Therefore, the output is logic `1’ for P = 0, Q = 1 and P = 1, Q = 0. Therefore, the output is

F = \bar P Q +P \bar Q = XOR (P, Q)

Ans. (d)

Related Answered Questions

Question: 25.SG.Q.13

The output Y of a two-bit comparator is logic 1 whenever the two-bit input A is greater than the two-bit input B. The number of combinations for which the output is logic 1, is  (a) 4 (b) 6 (c) 8 (d) 10 ...

Verified Answer:

Output will be 1 if A > B. Now, A can be greate...
Question: 25.SG.Q.11

The Boolean function realized by the logic circuit shown in the following figure is  (a) F = ∑ m (0, 1, 3, 5, 9, 10, 14) (b) F = ∑ m (2, 3, 5, 7, 8, 12, 13) (c) F = ∑ m (1, 2, 4, 5, 11, 14, 15) (d) F = ∑ m (2, 3, 5, 7, 8, 9, 12) ...

Verified Answer:

\begin{aligned} F(A, B, C, D)= & \bar{...
Question: 25.SG.Q.10

What are the minimum number of 2-to-1 multiplexers required to generate a two-input AND gate and a two-input EX-OR gate? (a) 1 and 2 (b) 1 and 3 (c) 1 and 1 (d) 2 and 2 ...

Verified Answer:

One 2-to-1 multiplexer is required to implement AN...
Question: 25.SG.Q.9

What are the minimum numbers of NOT gates and two-input OR gates required designing the logic of the driver for this seven-segment display? (a) 3 NOT and 4 OR (b) 2 NOT and 4 OR (c) 1 NOT and 3 OR (d) 2 NOT and 3 OR ...

Verified Answer:

The answer is obvious from the Boolean functions o...
Question: 25.SG.Q.8

If segments a to g are considered as functions of P1 and P2 , then which of the following is correct? (a) g = P1 + P2, d = c +e (b) g = P1 + P2, d = c +e (c) g = P1 + P2, e = b + c, (d) g = P1 + P2, e = b + c ...

Verified Answer:

The truth table can be drawn as follows: \...
Question: 25.SG.Q.7

For the circuit shown in the following figure, I0 to I3 are the inputs to the 4:1 multiplexer R(MSB) and S are control bits. The output Z can be represented by (a) PQ + PQS +QRS (b) PQ + PQR +PQS (c) PQR +PQR +PQRS +QRS (d) PQR +PQRS +PQRS +QRS ...

Verified Answer:

The output can be written as Z = PRS + PQR\...
Question: 25.SG.Q.6

In the circuit shown in the following figure, X is given by (a) X = ABC + ABC + ABC + ABC (b) X = AB + BC + AC (c) X = AB + BC + AC (d) X = AB + BC + AC ...

Verified Answer:

Let the output of the first MUX be Y. Therefore, [...
Question: 25.SG.Q.5

The Boolean function f implemented in the following figure using two input multiplexers is (a) ABC + ABC (b) ABC + ABC (c) ABC + ABC (d) ABC + ABC ...

Verified Answer:

We know that f = E · A where E = \bar BC + ...
Question: 25.SG.Q.4

The minimum number of 2-to-1 multiplexers required to realize a 4-to-1 multiplexer is(a) 1 (b) 2 (c) 3 (d) 4 ...

Verified Answer:

Two 2-to-1 multiplexers are required at the input ...
Question: 25.SG.Q.3

The circuit shown in the following figure converts (a) BCD to binary code (b) Binary to excess —3 code (c) Excess —3 to Gray code (d) Gray to Binary code ...

Verified Answer:

The logic circuit is redrawn as shown in the follo...