Question 9.41: What are the advantages of CMOS logic?...

The main advantage of integrated circuit CMOS logic over all other logic systems is its extremely low power dissipation. At a maximum of 10  \mathrm{nW} per gate, the low dissipation allows greater circuit density within a given size of IC package. The resultant low supply current demand also makes CMOS ideal for battery-operated instruments. Typical supply voltages employed for CMOS are 5-10 \mathrm{~V}; however, operation with a supply of 1-18 \mathrm{~V} is possible. The circuitry is immune to noise levels as high as 30 \% of the supply voltage. The extremely high input resistance of MOSFETs gives CMOS gates typical input resistances of 10^{9} \Omega, and this makes it possible to have fan-outs greater than 50. Typical propagation delay time for CMOS is 25 \mathrm{~ns}. As in the case of NMOS and PMOS, the relatively low switching time is due to the high output resistance.

The logic 0 and logic 1 levels for CMOS are typically 30 and 70 \% of V_{D D}, respectively. With a 5 \mathrm{~V} supply, this gives V_{I H(\min )}=3.5 \mathrm{~V} and V_{I L(\max )}=1.5 \mathrm{~V}. CMOS gates draw virtually zero input current. Therefore, even with a large number of gate inputs connected to one output, the output voltages are V_{O H(\min )} \approx V_{D D}, and V_{O L(\max )} \approx 0.