With the help of a diagram describe a paralle-ladder using NAND gates.
Parallel addition of two numbers can be carried out by having a full-adder for each pair of bits that must be added, except for the least significant bits, which require only a half adder. To add two 8-bit numbers in parallel would require seven full adders plus a half adder.
In adder circuit using NAND gates, Fig. 10.15, it is apparent that the construction of a parallel 8-bit adder would be quite complicated. N-bit adders are available as integrated circuits, but once constructed, a parallel adder is limited to the size of numbers it can handle. An 8-bit adder cannot handle 9-bit numbers.