Question 9.38: With the help of suitable illustrations, describe the workin......
With the help of suitable illustrations, describe the working of NMOS NAND and NOR gates.
The circuits for NMOS NAND and NOR gates are shown in Fig. 9.36. Note that Q_{1} has a channel resistance (or R_{D(\text { on) }} value) of around 100 \mathrm{k} \Omega, while the R_{D(\text { on })} value for each of Q_{2} and Q_{3} is on the order of 1 \mathrm{k} \Omega. Also, in both cases, the gate of Q_{1} is biased to its drain terminal. When the source terminal of Q_{1} is lower than V_{D D}, the gate is positive with respect to the source. This is the condition necessary to bias Q_{1} ON. Consequently, Q_{1} is always in the O N condition, and its R_{D(o n)} acts as a load resistor for Q_{2} and Q_{3}.
Consider the circuit of Fig. 9.36(a). When input A and input B are LOW (near ground) transistors Q_{2} and Q_{3} are both OFF. No drain current flows, and there is no voltage drop across Q_{1}. The output voltage at this time is a HIGH level close of +V_{D D}. When HIGH (positive) input is applied to the gate of Q_{3}, Q_{3} tends to switch ON. However, with the gate of Q_{2} still held near ground, Q_{2} remains an open circuit and the output remains at its HIGH level. When HIGH inputs are applied to the gates of Q_{2} and Q_{3}, both transistors are switched \mathrm{ON}, and current flows through the channels of all three transistors. The total R_{D(\mathrm{on})} of Q_{2} and Q_{3} adds up to about 2 \mathrm{k} \Omega, while that of Q_{1} is around 100 \mathrm{k} \Omega. Therefore, the voltage drop across Q_{2} and Q_{3} is much smaller than that across Q_{1}, and the output voltage is now at a LOW level.
It is seen that the circuit performs as a NAND gate. When any one of the inputs is LOW, the output is HIGH. When input A AND input B are HIGH, the output voltage is LOW. As already stated, a PMOS NAND gate is exactly similar to the circuit in Fig. 9.36(a), except that V_{D D} must be negative and P-channel devices are used.
An NMOS NOR gate circuit is shown in Fig. 9.36(b). When both input levels are LOW, Q_{2} and Q_{3} are OFF. At this time the voltage drop across Q_{1} is almost zero and the output voltage is HIGH, close to V_{D D}. When a HIGH (positive) input is applied to terminals A OR terminal B, Q_{2} or Q_{3} switches ON, causing current to flow through Q_{1}. The voltage drop across either Q_{2} or Q_{3} (or both) is much smaller than that across Q_{1}, since the R_{D(\text { on) }} of Q_{1} is around 100 \mathrm{k} \Omega, while R_{D(\text { on) }} for Q_{2} and Q_{3} is approximately 1 \mathrm{k} \Omega. Therefore, when a HIGH input is applied to terminal A OR terminal B, the output voltage goes to a LOW level. A PMOS NOR gate is exactly similar to the circuit of Fig. 9.36(b), except that V_{D D} must be a negative quantity and \mathrm{P}-channel devices are used.
