Question 18.3: A D/A converter incorporates N equal current sources impleme...
A D/A converter incorporates N equal current sources implemented as NMOS devices, each having an aspect ratio of W/L [Fig. 18.23(a)]. Assuming that the interconnect between every two consecutive current sources has a small resistance, r, estimate the mismatch between I_N \text { and } I_1 .
If r is sufficiently small, the circuit can be modeled as shown in Fig. 18.23(b), where I_1 \approx I_2 \approx \cdots \approx I_N=I . The voltage at node N is obtained by superposition of currents:
\begin{aligned} V_N &=I r+I(2 r)+\cdots+I(N r) &(18.5)\\ &=\frac{N(N+1)}{2} \operatorname{Ir}&(18.6) \end{aligned}If V_N is relatively small, the assumption that I_1 \approx I_2 \approx \cdots \approx I_N used in the above calculation is reasonable and M_1-M_N exhibit roughly equal transconductances. Thus,
\begin{aligned} I_N &=I-g_m V_N &(18.7)\\ &=I-g_m r \frac{N(N+1)}{2} I &(18.8)\\ &=I\left[1-g_m r \frac{N(N+1)}{2}\right]&(18.9) \end{aligned}Since V_1 \approx N \cdot I \cdot r , we have I_1=I-g_m N \cdot I \cdot r , and the relative mismatch between I_1 \text { and } I_N is
\left|\frac{I_1-I_N}{I}\right|=g_m r \frac{N(N-1)}{2} (18.10)
The key point here is that the error grows in proportion to N^2 . The ground bus must therefore be sufficiently wide to minimize r.