AN NMOS CURRENT SOURCE Objective: Design an NMOS current source circuit to provide a specified bias current and output resistance. Specifications: Design an NMOS current source to provide a bias current of IQ = 100 µA and an output resistance greater than 20 MΩ. The reference current is to be IREF

Question

AN NMOS CURRENT SOURCE

Objective: Design an NMOS current source circuit to provide a specified bias current and output resistance.

Specifications: Design an NMOS current source to provide a bias current of [latex]I_{Q} = 100 µA[/latex] and an output resistance greater than 20 MΩ. The reference current is to be [latex]I_{REF} = 150 µA[/latex]. The circuit is to be biased at ±3.3 V and the voltage at the drain of the current source transistor is to be no smaller than −2.2 V.

Design Approach: A simple two-transistor current source would yield an output resistance of
[latex]R_{o} = r_{o} = \frac{1}{λ I_{Q}} = \frac{1}{(0.01)(0.1)} ⇒ 1 MΩ [/latex]
Therefore, to obtain a larger output resistance, a cascode current source is required. The basic circuit is shown in Figure 10.42. The transistor M₅ may actually need to be two or more transistors in series.
Choices: NMOS transistors are available with the following parameters: [latex]V_{T N} = 0.5 V, k_{n}^\prime = 80 µA/V²[/latex] , and [latex]λ = 0.01 V^{−1}[/latex]. The minimum width-to-length ratio ofany transistor is to be unity.

Accepted Answer

The minimum voltage [latex]V_{D3}[/latex] is to be −2.2 V. This voltage is given by
[latex]V_{D3} = V_{GS1} + V_{DS3}(sat) + V^{−} = V_{GS1} + V_{GS3} − V_{T N} + V^{−}[/latex]
Assuming that [latex]M_{1}[/latex] and [latex]M_{3}[/latex] are matched, we find
[latex]V_{D3} = −2.2 = 2V_{GS1} − 0.5 + (−3.3)[/latex]
or
[latex]V_{GS1} = V_{GS3} = 0.8 V[/latex]
Now
[latex]I_{Q} = \frac{k_{n}^\prime}{2} \frac{W}{L} (V_{GS1} − V_{T N})^{2}[/latex]
or
[latex]100 = \frac{80}{2} \left(\frac{W}{L} \right)_{1} (0.8 − 0.5)^{2}[/latex]
which yields

[latex]\left(\frac{W}{L} \right)_{1} = 27.8[/latex]
If we set

[latex]\left(\frac{W}{L} \right)_{1} = \left(\frac{W}{L} \right)_{3} = 28[/latex]
then we find that [latex]V_{GS1} = V_{GS3} = 0.799 V[/latex] and [latex]V_{D3}(min) = −2.202 V[/latex].

Assuming that [latex]M_{2}[/latex] and [latex]M_{4}[/latex] are matched, we have

[latex]\frac{I_{REF}}{I_{Q}} = \frac{(W/L)_{2}}{(W/L)_{1}} [/latex]
or
[latex]\frac{150}{100} = \frac{(W/L)_{2}}{28}[/latex]
which yields

[latex]\left(\frac{W}{L} \right)_{2} = \left(\frac{W}{L} \right)_{4} = 42[/latex]
Now the equivalent [latex]V_{GS5}[/latex] is given by
[latex]V_{GS5} = V^{+} − 2V_{GS2} − V^{−} = 3.3 − 2(0.799) − (−3.3)[/latex]
or
[latex]V_{GS5} = 5.0 V[/latex]
The width-to-length ratio is found from
[latex]I_{REF} = 150 = \frac{80}{2} \left(\frac{W}{L} \right)_{5} (5.0 − 0.5)^{2}[/latex]
which yields [latex](W/L)_{5} = 0.185[/latex]. A width-to-length ratio less than unity is unacceptable. Putting two equivalent [latex]M_{5}[/latex] transistors in series yields a gate-to-source voltage of [latex]V_{GS5} = 5.0/2 V[/latex]. Then
[latex]I_{REF} = 150 = \frac{80}{2} \left(\frac{W}{L} \right)_{5} \left(\frac{5.0}{2} − 0.5 \right)^{2}[/latex]

which yields [latex](W/L)_{5} = 0.938[/latex]. This value is still less than unity. Putting three equivalent [latex]M_{5}[/latex] transistors in series yields a gate-to-source voltage of [latex]V_{GS5} = 5.0/3 V[/latex]. Then
[latex]I_{REF} = 150 = \frac{80}{2} \left(\frac{W}{L} \right)_{5} \left(\frac{5.0}{3} − 0.5 \right)^{2}[/latex]

which yields [latex](W/L)_{5} = 2.76[/latex]. This is an acceptable solution.
The output resistance is given by
[latex]R_{o} = r_{o3} + r_{o1}(1 + g_{m3} r_{o3})[/latex]
We find
[latex]r_{o1} = r_{o3} = \frac{1}{λ I_{Q}} = \frac{1}{(0.01)(0.1)} ⇒ 1 MΩ[/latex]
and
[latex]g_{m3} = 2 \sqrt{\frac{k_{n}^\prime}{2} \left(\frac{W}{L} \right)_{3} I_{Q}} = 2 \sqrt{\left( \frac{80}{2} \right)(28)(100)} = 669 µA/V[/latex]
We then find
[latex]R_{o} = 1 + 1 [1 + (669)(1)] = 671 M \Omega[/latex]
This value certainly meets the design criteria.

Comment: The very large output resistance of 671 MΩ assumes that we have ideal MOS transistors. In fact there are leakage currents that, in reality, will lower the output resistance. However, the cascode current source does provide a very high output resistance that is useful in differential amplifiers as we will see in Chapter 11.

Question 10.DA.5: AN NMOS CURRENT SOURCE Objective: Design an NMOS current sou...

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