Question 9.4: Design a counter with the irregular binary count sequence sh...

Design a counter with the irregular binary count sequence shown in the state diagram of Figure 9–30. Use D flip-flops.

Figure 9.30
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Step 1: The state diagram is as shown. Although there are only four states, a 3-bit counter is required to implement this sequence because the maximum binary count is seven. Since the required sequence does not include all the possible binary states, the invalid states (0, 3, 4, and 6) can be treated as “don’t cares” in the design. However, if the counter should erroneously get into an invalid state, you must make sure that it goes back to a valid state.

Step 2: The next-state table is developed from the state diagram and is given in Table 9–10.

Step 3: The transition table for the D flip-flop is shown in Table 9–11.

Step 4: The D inputs are plotted on the present-state Karnaugh maps in Figure 9–31.
Also “don’t cares” can be placed in the cells corresponding to the invalid
states of 000, 011, 100, and 110, as indicated by the red Xs.

Step 5: Group the 1s, taking advantage of as many of the “don’t care” states as possible for maximum simplification, as shown in Figure 9–31. The expression for each D input taken from the maps is as follows:

D_{0}  =  \overline{Q_{0}}  +  Q_{2}

 

D_{1}  =  \overline{Q_{1}}

 

D_{2}  =  \overline{Q_{0}}  +  Q_{2} \overline{Q_{1}}

Step 6: The implementation of the counter is shown in Figure 9–32.

An analysis shows that if the counter, by accident, gets into one of the invalid states (0, 3, 4, 6), it will always return to a valid state according to the following sequences: 0 → 3 → 4 → 7, and 6 → 1.

TABLE 9–10
Next-state table.

Present State

Next State
Q_{2} Q_{1} Q_{0} Q_{2} Q_{1}

Q_{0}

0

0 1 0 1 0
0 1 0 1 0

1

1

0 1 1 1 1
1 1 1 0 0

1

 

TABLE 9–11
Transition table for a D flip-flop.

Output Transitions

Flip-Flop Input
Q_{N} Q_{N + 1}

D

0

\longrightarrow 0 0
0 \longrightarrow 1

1

1

\longrightarrow 0 0
1 \longrightarrow 1

1

Figure 9.31
Figure 9.32

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