Question 18.18: Sketch the output waveform for the circuit shown in Fig. 18....
Sketch the output waveform for the circuit shown in Fig. 18.55. It is given that discharging time constant (CR_L) is much greater than the time period of input wave.
During positive half-cycle of the input signal, the diode is forward biased. The network will appear as shown in Fig. 18.56. It is clear that V_{\text {out }}= + 2 V. Further, applying Kirchhoff’s voltage law to the input loop in Fig. 18.56, we have,
5 \,V -V_C-2 \,V =0
∴ V_C=3 \,V
Therefore, the capacitor will charge up to 3 V.
During the negative half-cycle of the input signal, the diode is reverse biased and will behave as an open [See Fig. 18.57]. Now battery of 2 V has no effect on V_{\text {out }}.
Applying Kirchhoff’s voltage law to the outside loop of Fig. 18.57, we have,
-5-3-V_{\text {out }}=0
or V_{\text {out }}=-8 \,V
The negative sign results from the fact that the polarity of 8 V is opposite to the polarity defined for V_{\text {out }}. The clamped output is shown in Fig. 18.58. Note that the output swing of 10 V matches with the input swing.
Note. It is a biased clamper circuit. It allows a waveform to be shifted above or below (depending upon the polairty of 2 V battery) a dc reference other than 0 V.
