Question 18.19: Sketch the output waveform for the circuit shown in Fig. 18....
Sketch the output waveform for the circuit shown in Fig. 18.59. It is given that discharging time constant (= CR_L) is much greater than the time period of input wave.
During the positive half-cycle of input signal, the diode is forward biased. Therefore, the diode behaves as a short [See Fig. 18.60]. It is easy to see that V_{\text {out }}=-2 V. Further, applying Kirchhoff’s voltage law to the input loop [ See Fig. 18.60], we have,
5\, V-V_C+2\, V =0
or V_C=7\, V
Therefore, the capacitor will charge upto 7 V.
During the negative half-cycle of the input signal, the diode is reverse biased and behaves as an open as shown in Fig. 18.61. Now battery of 2 V has no effect on V_{out}. Applying Kirchhoff ’s voltage law to the outside loop of Fig. 18.61, we have,
-5 \,V -7 \,V -V_{\text {out }}=0
or V_{\text {out }}=-12 \,V
The negative sign results from the fact that the polarity of 12 V is opposite to the polarity defined for V_{out}. The clamped output is shown in Fig. 18.62. Note that output and input swings are the same.
