Question 9.11: A CMOS inverter has a total inherent drain capacitance at th...

Before any load is added (i.e. with 1 pF inherent capacitance) the inherent propagation delay of this inverter can be calculated from Equation 9.4: τ_{p}=2C_{L}/KV_{dd} . Now, since K_{N} =K_{P} then the high-to-low delay will equal the low-to-high delay and it does not matter which of the two we use. Hence

As external load capacitance is added the propagation delay will increase linearly at a rate of 6.25 ns/pF. A graph of propagation delay versus external load capacitance can be plotted and is shown in Fig. 9.12. The graph does not pass through the zero delay point since the intercept on the y-axis is the inherent delay before any external load is added. If we wish to decrease the delay of a CMOS gate then we must do one of two things. Either decrease the capacitance or increase K. The capacitance is decreased by reducing the size of the devices but this is limited to the minimum linewidth* achievable with the process. Hence if the designer is already at the limit of the process then all that remains is to increase K which is implemented by increasing the W/L ratio.

Note: It is also possible with some CMOS processes to reduce delays by either increasing V_{dd} (you should check the data sheet before doing this!) or by reducing the temperature (this results in an increase in mobility and hence an increase in K).

* The minimum linewidth is the narrowest feature that an IC manufacturing process can produce. The smaller the feature size the more transistors per unit area.