A CMOS version of a three-state logic output buffer is shown in Fig. 9.30. Explain how the circuit operates.
Question 9.21: A CMOS version of a three-state logic output buffer is shown...
With the control line high, a logic ‘l’ appears at the gate of the PMOS and a logic ‘0’ at the gate of the NMOS. Hence both the PMOS and NMOS transistors are turned off and the output presents a high impedance. However, when the control line is low the data at D can pass through to the output and the gate operates normally.
Related Answered Questions
Total load from 15 CMOS devices= 15×10 pF = 150 pF...
Since the input current to a 74ACT device is negli...
From Table 9.1 the output current drive of a 74ACT...
NM_{H}=V_{OHmin}-V_{IHmin}=4.3-2.0=2.3V[/la...
From Equation 9.3:P_{dynamic}=C_{L}×V_{dd}^...
Using the above rules we concentrate on the NMOS n...
Fig. 9.13 (a): with either A or B or both high the...