A single cell of an SRAM uses 20 MΩ load resistors. If the chip operates at 5 V and contains 64 Kbits then what is its power consumption? Assume that the voltage across an MOS transistor when on is 0 V.
A single cell of an SRAM uses 20 MΩ load resistors. If the chip operates at 5 V and contains 64 Kbits then what is its power consumption? Assume that the voltage across an MOS transistor when on is 0 V.
When one of the inverter outputs is low then current flows through the load resistor from V_{dd} to V_{ss}. The power consumed for one cell is thus
V_{dd}^{2}/20×10^{6}=1.25μW
Hence for a 64Kbit SRAM the total power consumed is 80 mW. Notice that if the power supply is reduced to 2 V then the total power consumed reduces to 12.8 mW. If CMOS is used this static power consumption is reduced but with the added disadvantage of a lower packing density due to more transistors per bit.