Consider the circuit in Fig. 7.47a, where a dc power supply, typically fed from a wall outlet, is modeled as a dc voltage source in series with a resistor RS. The load draws a constant current and is modeled as a current source. We wish to design the simplest possible circuit that will isolate the

Question

Consider the circuit in Fig. 7.47a, where a dc power supply, typically fed from a wall outlet, is modeled as a dc voltage source in series with a resistor [latex]R_{S}[/latex]. The load draws a constant current and is modeled as a current source. We wish to design the simplest possible circuit that will isolate the load device from disturbances in the power supply voltage. In effect, our task is to improve the performance of the power supply at very little additional cost.
A standard solution to this problem involves the use of a capacitor [latex]C_{D}[/latex], as shown in Fig. 7.47b. The two voltage sources and the single-pole double-throw switch model the input disturbance sketched in Fig. 7.47c. Engineers call [latex]C_{D}[/latex] a decoupling capacitor since it decouples disturbances in the input voltage from the output voltage. In typical electronic circuits, we find liberal use of these decoupling capacitors. Thus, our task is to develop a design equation for [latex]C_{D}[/latex] in terms of [latex]R_{S}, V_{S}, V_{o}, ΔV_{S}, ΔV_{o},[/latex] and t′. Our result will be applicable to any scenario that can be modeled by the circuit in Fig. 7.47b.

Accepted Answer

The voltage across [latex]C_{D}[/latex] can be expressed in the standard form as

[latex]v_{o}(t) = K_{1} + K_{2}e^{-t/ au}[/latex] 7.41

Equivalent circuits for t = 0 and t = [latex]\infty[/latex] are shown in Fig. 7.48a and b, respectively. At these two time extremes we find

[latex]v_{o}(0) = K_{1} + K_{2} = V_{S} - I_{L} R_{S}[/latex]
[latex]v_{o}(\infty) = K_{1} = V_{S} + ΔV_{S} - I_{L}R_{S}[/latex] 7.42

To determine the time constant’s equivalent resistance, we return to the circuit in Fig. 7.48b, reduce all independent sources to zero, and view the resulting circuit from the capacitor’s terminals. It is easy to see that the time constant is simply [latex]R_{S}C_{D}[/latex]. Thus,

[latex]v_{o}(t) = V_{S} + ΔV_{S} - I_{L}R_{S} - ΔV_{S} e^{-t/R_{S}C_{D}}[/latex] 7.43

At exactly t = t′, the output voltage is its original value, [latex]V_{o}[/latex](0) plus Δ[latex]V_{o}[/latex]. Substituting this condition into Eq. (7.43) yields

[latex]v_{o}(t^{\prime}) = V_{S}- I_{L}R_{S} + ΔV_{o} = V_{S} + ΔV_{S} - I_{L}R_{S} - ΔV_{S} e^{-t^{\prime}/R_{S}C_{D}}[/latex]

which can be reduced to the expression

[latex]ΔV_{S} - ΔV_{o} = ΔV_{S}e^{-t^{\prime}/R_{S}C_{D}}[/latex] 7.44

Notice that the value of [latex]C_{D}[/latex] depends not on the input and output voltages, but rather on the changes in those voltages! This makes Eq. (7.44) very versatile indeed. A simple algebraic manipulation of Eq. (7.44) yields the design equation for [latex]C_{D}[/latex]:

[latex]C_{D} =\frac{t^{\prime}}{R_{S}\,ln\Big[ \frac{ΔV_{S}}{ΔV_{S} - ΔV_{o}}\Big] }[/latex] 7.45

Examining this expression, we see that [latex]C_{D}[/latex] is directly related to t′ and inversely related to [latex]R_{S}[/latex]. If t′ doubles or if [latex]R_{S}[/latex] is halved, then [latex]C_{D}[/latex] will double as well. This result is not very surprising. The dependence on the voltage changes is more complex. Let us isolate this term and express it as

[latex]f =\frac{1}{ln \Big[ \frac{ΔV_{S}}{ΔV_{S} - ΔV_{o}} \Big]} =\frac{1}{ln \Big[ \frac{1}{1- ΔV_{o}/ΔV_{S}} \Big]} = \frac{-1}{ln \Big[ 1 -\frac{ΔV_{o}}{ΔV_{S}}\Big]}[/latex] 7.46

Figure 7.49 shows a plot of this term versus the ratio [latex]ΔV_{o}/ΔV_{S}[/latex]. Note that for very small [latex]ΔV_{o}[/latex] (i.e., a large degree of decoupling), this term is very large. Since this term is multiplied with t′ in Eq. (7.45), we find that the price for excellent decoupling is a very large capacitance.

Finally, as an example, consider the scenario in which [latex]V_{S}[/latex] is 5 V, [latex]R_{S}[/latex] is 20 Ω, and the input disturbance is characterized by [latex]ΔV_{S}[/latex] = 1 V and t′ = 0.5 ms. If the output changes are to be limited to only 0.2 V, the required capacitance would be [latex]C_{D}[/latex] = 112.0 μF. Such a capacitor rated for operation at up to 16 V costs less than $0.20 and should be slightly smaller than a peanut M&M.
This very simple, but very important, application demonstrates how an engineer can apply his or her basic circuit analysis skills to attack and describe a practical application in such a way that the result is broadly applicable. Remember, the key to this entire exercise is the creation of a circuit model for the decoupling scenario.

Question 7.19: Consider the circuit in Fig. 7.47a, where a dc power supply,...

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