Construct a 4-to-16 line decoder with two 3-to-8 line decoders having active LOW ENABLE inputs

Question

Construct a [latex]4-to-16[/latex] line decoder with two [latex]3-to-8[/latex] line decoders having active LOW ENABLE inputs

Accepted Answer

Let us assume that [latex]A (LSB), B, C[/latex] and [latex]D (MSB)[/latex] are the input variables for the [latex]4- to-16[/latex] line decoder. Following the steps outlined earlier, [latex]A (LSB), B[/latex] and [latex]C (MSB)[/latex] will then be the input variables for the two [latex]3- to-8[/latex] line decoders. If we recall the [latex]16[/latex] possible input combinations from [latex]0000[/latex] to[latex] 1111[/latex] in the case of a [latex]4-to-16[/latex] line decoder, we find that the first eight combinations have [latex]D = 0[/latex], with CBA going through [latex]000[/latex] to [latex]111[/latex]. The higher-order eight combinations all have[latex] D = 1[/latex], with CBA going through [latex]000[/latex] to [latex]111[/latex]. If we use the D-bit as the ENABLE input for the less significant [latex]3-to-8[/latex] line decoder and the [latex]\overline{D} [/latex]-bit as the ENABLE input for the more significant [latex]3-to-8[/latex] line decoder, the less significant [latex]3-to-8[/latex] line decoder will be enabled for the less significant eight of the 16 input combinations, and the more significant [latex]3-to-8[/latex] line decoder will be enabled for the more significant of the [latex]16[/latex] input combinations. Figure 8.24 shows the hardware implementation. One of the output lines [latex]D_0[/latex] to [latex]D_{15}[/latex] is activated as the input bit sequence DCBA goes through 0000 to [latex]1111[/latex].

Question 8.8: Construct a 4-to-16 line decoder with two 3-to-8 line decode...

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