Design a 16-to-1 multiplexer using two 8-to-1 multiplexers having an active LOW ENABLE input.

Question

Design a [latex]16-to-1[/latex] multiplexer using two [latex]8-to-1[/latex] multiplexers having an active LOW ENABLE input.

Accepted Answer

A [latex]16-to-1[/latex] multiplexer can be constructed from two [latex]8-to-1[/latex] multiplexers having an ENABLE input. The ENABLE input is taken as the fourth selection variable occupying the MSB position.
Figure 8.14 shows the complete logic circuit diagram. IC 74151 can be used to implement an [latex]8-to-1[/latex]
multiplexer.

The circuit functions as follows. When [latex]S_{3}[/latex] is in logic ‘[latex]0[/latex]’ state, the upper multiplexer is enabled and the lower multiplexer is disabled. If we recall the truth table of a four-variable Boolean function, [latex]S_{3}[/latex] would be ‘[latex]0[/latex]’ for the first eight entries and ‘[latex]1[/latex]’ for the remaining eight entries. Therefore, when [latex]S_{3}= 0[/latex] the final output will be any of the inputs from [latex]D_{0}[/latex] to[latex]D_{7}[/latex] , depending upon the logic status of [latex]S_{2} , S_{1} [/latex] and S0. Similarly, when [latex]S_{3} = 1[/latex] the final output will be any of the inputs from[latex]D_{8}[/latex] to [latex]D_{15}[/latex] , again depending upon the logic status of [latex]S_{2}[/latex] , [latex]S_{1}[/latex] and S0. The circuit therefore implements the truth table of a [latex]16[/latex]-to-[latex]1[/latex] multiplexer.

Question 8.3: Design a 16-to-1 multiplexer using two 8-to-1 multiplexers h...

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