Draw a NAND gate and its dual and describe their outputs in terms of assertion level logic.
Draw a NAND gate and its dual and describe their outputs in terms of assertion level logic.
These are shown in Fig. 1.18. In the NAND form the output is active-LOW (because of the bubble) if both inputs are active-HIGH. In its dualled (OR) form the output is active-HIGH if either input is active-LOW (because of the bubbles). The two forms effectively describe the neccesary conditions for outputs of 0 (LOW) and 1 (HIGH) respectively from the circuit.