Question 7.21: Examine the 74HC165 function table and determine (a) the con...

(a) The first entry in the table shows that the {SH}/{\overline{LD}} input has to be LOW for the parallel load operation. When this input is LOW, the data present at the P inputs are asynchronously loaded into the register FFs, independent of the CP and the CP INH inputs. Of course, only the outputs from the last FF are externally available.
(b) The shifting operation cannot take place unless the {SH}/{\overline{LD}} input is HIGH and a PGT occurs at CP while CP INH is LOW [see the fourth table entry in Figure 7-71(b)]. A HIGH at CP INH will inhibit the effect of any clock pulses. Note that the roles of the CP and CP INH inputs can be reversed, as indicated by the last table entry, because these two signals are ORed together inside the IC.