Figure 8.13 shows the use of an 8-to-1 multiplexer to implement a certain four-variable Boolean function. From the given logic circuit arrangement, derive the Boolean expression implemented by the given circuit.

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Accepted Answer

This problem can be solved by simply working backwards in the procedure outlined earlier for designing the multiplexer-based logic circuit for a given Boolean function. Here, the hardware implementation is known and the objective is to determine the corresponding Boolean expression.

From the given logic circuit, we can draw the implementation table as given in Table 8.7. The entries in the first row [latex](0, 1, 2, 3, 4, 5, 6, 7)[/latex] and the second row [latex](8, 9, 10, 11, 12, 13, 14, 15)[/latex] are so because the selection variable chosen for application to the inputs is the MSB variable D. Entries in the first row include all those minterms that contain D, and entries in the second row include all those minterms that contain D. After writing the entries in the first two rows, the entries in the third row can be filled in by examining the logic status of different input lines in the given logic circuit diagram. Having completed the third row, relevant entries in the first and second rows are highlighted.

The Boolean expression can now be written as follows:

[latex]Y=\sum{2,4,9,10}=\overline{D}.\overline{C}.B.\overline{A}+ \overline{D}.C.\overline{B}.\overline{A}+ D.\overline{C}.\overline{B}.A+ D.\overline{C}.B.\overline{A}[/latex]

[latex]=\overline{C}.B.\overline{A}.\left( \overline{D}+ D\right)+ \overline{D}.C.\overline{B}.\overline{A}+ D.\overline{C}.\overline{B}.A[/latex]

[latex]=\overline{C}.B.\overline{A}+ \overline{D}.C.\overline{B}.\overline{A}+ D.\overline{C}.\overline{B}.A[/latex]

Table 8.7 Implementation table.
[latex]I_7[/latex]	[latex]I_6[/latex]	[latex]I_5[/latex]	[latex]I_4[/latex]	[latex]I_3[/latex]	[latex]I_2[/latex]	[latex]I_1[/latex]	[latex]I_0[/latex]
7	6	5	4	3	2	1	0	[latex]\overline{D} [/latex]
15	14	13	12	11	10	9	8	D
0	0	0	[latex]\overline{D} [/latex]	0	1	D	0

Table 8.7 Implementation table.
$I_7$	$I_6$	$I_5$	$I_4$	$I_3$	$I_2$	$I_1$	$I_0$
7	6	5	4	3	2	1	0	$\overline{D}$
15	14	13	12	11	10	9	8	D
0	0	0	$\overline{D}$	0	1	D	0

Question 8.2: Figure 8.13 shows the use of an 8-to-1 multiplexer to implem...

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