How would the truth table shown in Fig. 11.19(a) be implemented using a ROM?
Fig. 11.19(a) Truth table used in Example 11.7 for implementation in ROM
| A | B | C | D | X | Y | Z |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 0 | 0 | 0 | 1 | 1 | 0 | 1 |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 |
| 0 | 0 | 1 | 1 | 0 | 1 | 1 |
| 0 | 1 | 0 | 0 | 0 | 1 | 0 |
| 0 | 1 | 0 | 1 | 1 | 0 | 0 |
| 0 | 1 | 1 | 0 | 0 | 0 | 0 |
| 0 | 1 | 1 | 1 | 1 | 0 | 1 |
| 1 | 0 | 0 | 0 | 0 | 1 | 1 |
| 1 | 0 | 0 | 1 | 0 | 0 | 0 |
| 1 | 0 | 1 | 0 | 1 | 1 | 1 |
| 1 | 0 | 1 | 1 | 0 | 0 | 0 |
| 1 | 1 | 0 | 0 | 0 | 1 | 0 |
| 1 | 1 | 0 | 1 | 0 | 0 | 0 |
| 1 | 1 | 1 | 0 | 1 | 1 | 1 |
| 1 | 1 | 1 | 1 | 0 | 0 | 0 |
A ROM of at least size 16 x 3 would be needed. The four address lines would be connected to the input variables A, B, C and D with the three outputs providing X, Y and Z. The required outputs (three-bit word) for each of the 16 possible input combinations would be programmed into the ROM, straight from the truth table. This is shown in Fig. 11.19(b) for the first four addresses, where , and , are the nth address line and output respectively of the ROM.
Note that because all the fundamental product terms are produced by the fixed AND array of the ROM then no minimisation can take place.
Fig. 11.19(b) Truth table used in Example 11.7 for implementation in ROM
| A0 | A1 | A2 | A3 | O0 | O1 | O2 | |
| WORD 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| WORD 1 | 0 | 0 | 0 | 1 | 1 | 0 | 1 |
| WORD 2 | 0 | 0 | 1 | 0 | 0 | 0 | 0 |
| WORD 3 | 0 | 0 | 1 | 1 | 0 | 1 | 1 |