Question 7.11: Refer to Figure 7-15, where a 74HC160 has the input signals ...

Initially (at t_{0}) the counter’s FFs are all LOW. Since this is not the terminal state for the BCD counter, output RCO will also be LOW. The first PGT on the CLK input occurs at t_{1} and, since all control inputs are HIGH, the counter will increment to 0001. The counter continues to count up with each PGT until t_{2}. The asynchronous \overline{ CLR} input goes LOW at t_{2} and will immediately reset the counter to 0000 at that point. At t_{3}, the \overline{ CLR} input is still active (LOW), so the PGT of the CLK input will be ignored and the counter will stay at 0000. Later the \overline{ CLR} input goes inactive again and the counter will count up to 0001 and then to 0010. At t_{4}, the count enable ENP is LOW, so the count holds at 0010. For subsequent PGTs of the CLK input, the counter is enabled and counts up until t_{5}. The \overline{ LOAD} input is LOW for t_{5}. This will synchronously load the applied data value 0111 (7) into the counter at t_{5}. At t_{6}, the count enable ENT is LOW, so the count holds at 0111. For the two subsequent PGTs after t_{6}, the counter will continue counting up since it is re-enabled. At t_{7}, the BCD counter reaches its terminal state 1001 (9) and the RCO output now goes HIGH. At t_{8}, ENP is LOW and the counter stops counting (remaining at 1001). At t_{9}, while ENT is LOW, the RCO output will be disabled so that it returns to a LOW even though the counter is still at its terminal state (1001). Recall that only ENT controls the RCO output. When ENT returns HIGH during the counter’s terminal state, RCO goes HIGH again. At t_{10} the counter is enabled, and it recycles to 0000 and then counts to 0001 on the last PGT.