Question 7.12: Refer to Figure 7-17, where a 74HC190 has the input signals ...

Initially (at t_{0}), the counter’s FFs are all LOW. Since the counter is enabled (\overline{CTEN}=0) and the count direction control {D}/{\overline{U} }=0, the BCD counter will start counting up on the first PGT applied to CLK at t_{1} and continues to count up with each PGT until t_{2}, where the count has reached 0101. The asynchronous \overline{LOAD} input goes LOW at t_{2} and will immediately load 0111 into the counter at that point. At t_{3}, the \overline{LOAD} input is still active (LOW), so the PGT of the CLK input will be ignored and the counter will stay at 0111. Later the \overline{LOAD} input goes HIGH again and the counter will count up to 1000 at the next PGT. At t_{4}, the counter increments to 1001, which is the terminal state for a BCD up counter and the MAX/MIN output goes HIGH. During t_{5}, the counter is at its terminal state and the CLK input is LOW, so \overline{RCO} goes LOW. For subsequent PGTs of the CLK input, the counter recycles to 0000 and continues to count up until t_{6}. Just prior to t6, the {D}/{\overline{U} } control changes to a HIGH. This will make the counter count down at t_{6} and again at t_{7}, where it will be at state 0000, which now is the terminal state since we are counting down, and MAX/MIN will output a HIGH. During t_{8}, when the CLK input goes LOW, the \overline{RCO} output again will be LOW. At t_{9}, the counter is disabled with \overline{CTEN}=1 and the counter holds at 1001. For the subsequent CLK pulses, the counter continues to count down.