CMOS: Circuit Design, Layout, and Simulation 3rd. Edition by R. Jacob Baker | 9780470881323 | 0470881321 | Holooly

Electric Circuits

CMOS: Circuit Design, Layout, and Simulation

188 SOLVED PROBLEMS

Question: 30.2

Suppose that the 2R MSB resistor in the DAC described in Ex. 30.1 experiences a 0.5% mismatch. Estimate the resulting DAC’s INL and DNL. Use SPICE to verify your answer. ...

Verified Answer:

The 0.5% mismatch (ΔR/R or 1 σ [standard deviation...

Question: 30.6

Suppose perfect switches are available for the circuit of Fig. 30.26. Estimate the residual offset voltage in terms of the op-amp’s gain, AG, from the auxiliary port to the op-amp output. ...

Verified Answer:

If the offset voltage before reduction is

V...

Question: 30.1

Suppose a 10-bit, voltage-mode DAC with the topology seen in Fig. 30.14 is implemented where R = 10k and CL = 10 pF. Estimate the maximum clocking frequency that can be used to clock the register supplying the input words to the DAC. Verify your answer using SPICE. ...

Verified Answer:

For complete settling the DAC must be 10-bit accur...

Question: 30.8

Simulate the operation of the S/Hs shown in both Figs. 30.31 and 30.34. Assume the S/H is clocked at 100 MHz, νin+ is a sinewave that swings from ground to VDD, and νin- is connected to VCM(the input signal is single-ended and covers the entire supply range). Show how the op-amp’s input common-mode ...

Verified Answer:

Figure 30.35 shows the simulation results for the ...

Question: 23.4

Simulate the operation of the reference in Fig. 23.22 where the voltage across the diode is used as a reference voltage. Use a nominal reference current of 1 μA. ...

Verified Answer:

Using Eq. (23.23), we can set R to 700k. The simul...

Question: 30.23

Simulate the operation of the circuit shown in Fig. 30.69. This schematic is Fig. 30.66 redrawn with a 50 mV op-amp offset. ...

Verified Answer:

The simulation results are shown in Fig. 30.70. Fi...

Question: 30.21

Simulate the operation of the circuit shown in Fig. 30.66. Show the input and output signals as the difference between the two differential input signals. Assume the common-mode voltage coming out of the op-amp is precisely 500 mV. ...

Verified Answer:

The simulation results are shown in Fig. 30.67. No...

Question: 30.19

Simulate the operation of the circuit shown in Fig. 30.59 (a cascade of Figs. 30.55 and 30.56). Comment on the ideal outputs and the simulation results. ...

Verified Answer:

This circuit shows the same mismatched capacitors ...

Question: 22.7

Simulate the CMRR of the diff-amp in Fig. 22.12. Show that the CMRR falls with increasing frequency. ...

Verified Answer:

As mentioned above, the (low-frequency) calculated...

Question: 29.8

Show the value of the output voltage at the end of each cycle for a 6-bit cyclic DAC with an input value of D5D4D3D2D1D0 = 110101. Assume that VREF = 5 V. ...

Verified Answer:

We can predict the value of the output based on ou...

Loading...