If a differential pair is to be biased with \mathrm{I}_{\text {bias }}=200 \mu \mathrm{A} , how large must the devices be sized to ensure the input offset is less than 1 mV 99.8% of the time? Assume that \mathrm{A}_{\mathrm{Vt} 0}=4 \mathrm{mV} \cdot \mu \mathrm{m} \text { and } \mathrm{A}_{K^{\prime}}=0.01 \mu \mathrm{m}.
The specs require the input offset to have a standard deviation better than 1 \mathrm{mV} / 3=0.333 \mathrm{mV}. Each device has a nominal drain current of \mathrm{I}_{\mathrm{D}}=100 \mu \mathrm{A}. Assuming that the first term is dominant, equation (2.18) gives
\sigma^2\left(\mathrm{~V}_{\mathrm{os}}\right)=\frac{\sigma^2\left(\Delta \mathrm{I}_{\mathrm{D}}\right)}{\mathrm{g}_{\mathrm{m}}^2}=\frac{1}{\mathrm{WL}}\left[\mathrm{A}_{\mathrm{Vt0}}{ }^2+\left(\frac{\mathrm{I}_{\mathrm{D}}}{\mathrm{g}_{\mathrm{m}}}\right)^2 \mathrm{~A}_{K^′}{ }^2\right] (2.18)
(0.333 \mathrm{mV})^2 \cong \frac{(4 \mathrm{mV} \cdot \mu \mathrm{m})^2}{\mathrm{WL}} \Rightarrow \mathrm{WL}=144 \mu \mathrm{m}^2
For example, if the gate length is L = 0.5 μm , the device widths must be W = 288 μm.