Analog Integrated Circuit Design 2nd. Edition by Tony Chan Carusone; David Johns; Kenneth W Martin | 9780470770108 | 0470770104 | Holooly

Analog and Digital Signals and Systems

Analog Integrated Circuit Design

184 SOLVED PROBLEMS

Question: 19.16

What is the behavior of a ring with only n = 1 inverter, as shown in Fig. 19.19(a)? ...

Verified Answer:

Based upon (19.80)

f_{0} = \frac{1}{T_{0}}...

Question: 19.5

A PLL is to operate with a reference clock frequency of 10 MHz and an output frequency of 200 MHz. Design a loop filter for the charge-pump phase comparator so that the loop bandwidth is approximately 1 / 20th of the reference clock frequency and Q = 0.1. Assume the VCO has Kosc = 2π × 10^7 rad/Vs ...

Verified Answer:

From (19.32)

\omega _{pll} = \sqrt{\frac{K...

Question: 19.20

Consider the charge-pump PLL designed in Example 19.8 and consider its operation with N = 75 using the VCO in Example 19.18. Assume the 20-MHz PLL input (after the M = 2 divider) has a phase noise modeled by (19.86) with h0 = 10^-14 rad²/Hz, h2 = 10^-9 rad² · Hz, and h3 ≈ 0. What is the phase noise ...

Verified Answer:

The contribution of the reference input to the PLL...

Question: 19.19

A VCO with a phase noise given by SΦ, vco(f) = h2/f² is placed within an ideal second-order PLL. What is the resulting phase noise at the output? ...

Verified Answer:

For a second-order PLL, the open-loop gain L(s) is...

Question: 19.18

The P-cycle jitter of a VCO operating at 1.5 GHz is observed for different P to obtain a plot like Fig. 19.32 with Pc = 30. The P-cycle jitter over 10 cycles (P = 10) is 2.0 ps rms. Estimate the phase noise of the VCO using the model in (19.86) but neglecting the white-phase noise term h0, which ...

Verified Answer:

Substituting P = 10,

\sigma _{J(10)}= 2~ p...

Question: 19.17

What is the behavior of a ring of inverters with n = 2? ...

Verified Answer:

It is a bistable circuit meaning it has two stable...

Question: 19.15

It is desired to drive a digital system with a clock period that is always at least 1 ns. The clock has a nominal period T0 = 1.1 ns and a gaussian jitter distribution. If the rms period jitter is 5 ps, with what probability will any particular clock period be less than 1 ns? ...

Verified Answer:

The clock period will be less than 1 ns whenever t...

Question: 19.14

Find the PDF of τk for a sinusoid with amplitude A and angular frequency ω0 in additive white gaussian noise, n(t), with variance σn². ...

Verified Answer:

The sinusoid may be described as:

v(t) = A...

Question: 19.13

A clock’s zero crossings are modulated by a sinusoidal disturbance at a frequency fm so that Φk = Φ0sin(2πfmt) (19.71) What is the resulting rms absolute jitter, period jitter, and adjacent period jitter? ...

Verified Answer:

The phase noise

S_{\phi }^{2}(f)

...

Question: 19.12

What is the rms period jitter of the sinusoid in additive white noise from Example 19.9? ...

Verified Answer:

Again assuming the noise is much smaller than the ...

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