Question 5.1: A differential oscillator will be designed for f0 = 1.6 GHz....
A differential oscillator will be designed for f_0 = 1.6 GHz. The inductor to be used will be selected from a library in which there are 1 nH, 2 nH, 5 nH and 10 nH inductors with Q_{eff} = 7.
The transistors have characteristics similar to AMS 0.35 micron technology.
It is assumed that a 1 V bias voltage is available on the chip.
The allowed DC supply current is 2 mA.
The schematic of the circuit together with the tail current source is given in Fig. 5.6.
Since the output voltage swings around V_{DD}, the supply voltage must be chosen lower than the allowed maximum value by the expected amplitude of the oscillation with a safety margin, and must be checked later on.
We will use V_{DD} = 2.5 V, which corresponds to 1 V maximum amplitude, including the safety margin.
To obtain the oscillation with a relatively high negative resistance that corresponds
to a small transconductance (i.e., small supply current and small transistor width), the resonance impedance must be as high as possible.
Since the resonance impedance of the resonance circuit is R_p = L_{\omega_0}\times Q_{eff}, the first (seemingly obvious) choice would
have been to use the maximum inductance value, that is 10 + 10 = 20 nH in this case.
But this corresponds to a resonance capacitance that is equal to
Note that this capacitance represents the sum of (C_{gs}/2), (C_{db}/2), the resonance capacitor (or varactor), and the input capacitance of the following circuit which, on its own, can be in the range of several hundreds of femtofarads. Consequently, using the maximum inductance value would impose a very limited value for the total capacitance that may not be reasonable for practical applications.
In our case, it is preferable to work with a higher resonance capacitance that dictates the use of a 5 + 5 = 10 nH inductor, resonating at 1.6 GHz with 905 fF.
The effective parallel resistance of this resonance circuit at 1.6 GHz is
R_{eff}=L\omega_0Q_{eff}=10^{-8}\times (1.05\times 10^{10})\times 7=735 ohm
Since the circuit operates with a considerable safety margin, we can neglect the output resistance of the transistor and the losses of the resonance capacitance. The value of the negative resistance must be smaller than this theoretical value to guarantee sustained oscillation, so that the amplitude reaches the saturation end of the negative resistance curve.
Thus, we take r_o = – 350 ohms, which corresponds to g_m = 5.7 mS according to (5.6).
The aspect ratio to obtain this transconductance value with 1 mA drain DC current
can be calculated from (1.33):
Therefore the gate width must be 38 μm.
The gate width of the tail current source can be sized to conduct 2 mA under 1 V
gate bias voltage, which is found as 62 μm for 0.35 μm channel length.
The PSpice transient simulation file is given below:
*DIFFERENTIAL NEGATIVE RESISTANCE OSC.*
VDD 100 0 2.5
.LIB “CMOS7TM.MOD”
M1 1 2 3 0 MODN w=38u l=.35u ad=13.3e-8 as=13.3e-8 pd=40u
ps=40u nrd=.01 nrs=.01
M2 2 1 3 0 MODN w=38u l=.35u ad=13.3e-8 as=13.3e-8 pd=40u
ps=40u nrd=.01 nrs=.01
MT 3 4 0 0 MODN w=62u l=.35u ad=21.7e-8 as=21.7e-8 pd=70u
ps=70u nrd=.01 nrs=.01
VB 4 0 1
L1 1 11 5N
RL1 11 100 7.5
L2 2 22 5N
RL2 22 100 7.5
C 1 2 .9p
.IC v(1)=2.6v
.TRAN .03N 51N 50N .01N
.probe
.end
