Question 4.4: Objective: Design the bias of a MOSFET circuit such that the...

(dc design): The load line and the desired Q-point are given in Figure 4.18. If the Q-point is to be in the middle of the saturation region, the current at the transition point must be 4 mA.
The conductivity parameter is
K_{n} = \frac{k´_{n}}{2} \cdot \frac{W}{L} = \left(\frac{0.080}{2} \right) (25) = 1  mA/V^{2}

We can now calculate V_{DS} (sat) at the transition point. The subscript t indicates transition point values. To determine V_{GSt} , we use
I_{Dt} = 4 = K_{n}(V_{GSt}  −  V_{T N} )^{2} = 1(V_{GSt}  −  1)^{2}
which yields
V_{GSt} = 3  V
Therefore
V_{DSt} = V_{GSt}  −  V_{T N} = 3  −  1 = 2  V
If the Q-point is in the middle of the saturation region, then V_{DSQ} = 7  V, which would yield a 10 V peak-to-peak symmetrical output voltage. From Figure 4.17, we can write
V_{DSQ} = V_{DD}  −  I_{DQ} R_{D}
or
R_{D} = \frac{V_{DD}  −  V_{DSQ}}{I_{DQ}} = \frac{12  −  7}{2} = 2.5  k\Omega
We can determine the required quiescent gate-to-source voltage from the current equation, as follows:
I_{DQ} = 2 = K_{n}(V_{GSQ}  −  V_{T N} )^{2} = (1)(V_{GSQ}  −  1)^{2}
or
V_{GSQ} = 2.41  V
Then
V_{GSQ} = 2.41 = \left(\frac{R_{2}}{R_{1}  +  R_{2}} \right) (V_{DD}) = \left(\frac{1}{R_{1}} \right) \left( \frac{R_{1} R_{2}}{R_{1}  +  R_{2}} \right) (V_{DD})

= \frac{R_{i}}{R_{1}} \cdot V_{DD} = \frac{(100)(12)}{R_{1}}
which yields
R_{1} = 498  k \Omega and R_{2} = 125  k\Omega

(ac analysis): The small-signal transistor parameters are
g_{m} = 2 \sqrt{K_{n} I_{D Q}} = 2\sqrt{(1)(2)} = 2.83  mA/V
and
r_{o} = \frac{1}{λ I_{D Q}} = \frac{1}{(0.015)(2)} = 33.3  k\Omega
The small-signal equivalent circuit is the same as shown in Figure 4.7. The small-signal voltage gain is
A_{v} = \frac{V_{o}}{V_{i}} = −g_{m} (r_{o} || R_{D} ) = −(2.83)(33.3||2.5)
or
A_{v} = −6.58
Comment: Establishing the Q-point in the middle of the saturation region allows the maximum symmetrical swing in the output voltage, while keeping the transistor biased in the saturation region