Assuming λ = 0.2 μm, find the area and perimeters of junctions J_1, J_2 \text {, and } J_3 for the circuit in Fig. 2.16.
Since the width and length are shown as 10λ and 2λ, respectively, and λ = 0.2 μm, the physical sizes are W = 2 μm and L = 0.4 μm.
Thus, for junction J_1, using the formulas of (2.4) and (2.5), we have
\mathrm{A}_{\mathrm{s}}=\mathrm{A}_{\mathrm{d}}=5 \lambda \mathrm{W} (2.4)
\mathrm{P}_{\mathrm{s}}=\mathrm{P}_{\mathrm{d}}=10 \lambda+\mathrm{W} (2.5)
\mathrm{A}_{\mathrm{J} 1}=5 \lambda \mathrm{W}=5(0.2) 2 \mu \mathrm{m}^2=2 \mu \mathrm{m}^2 (2.6)
and
P_{J 1}=10 \lambda+W=[10(0.2)+2] \mu \mathrm{m}=4 \mu \mathrm{m} (2.7)
Since this junction is connected to ground, its parasitic capacitance is unimportant and little has been done to minimize its area. Contrast this case with junction J_2, where we have
A_{J 2}=2 \lambda W+12 \lambda^2=1.28 \mu \mathrm{m}^2 (2.8)
The perimeter is unchanged, resulting in \mathrm{P}_{\mathrm{J} 2}=4 \mu \mathrm{m} . Thus, we have decreased the junction area by using the fact that the transistor is much wider than the single contact used. However, sometimes wide transistors require additional contacts to minimize the contact impedance. For example, the two contacts used for junction J_1 result in roughly half the contact impedance of junction J_2.
Next, consider the shared junction. Here we have a junction area given by
A_{J 3}=2 \lambda W=0.8 \mu \mathrm{m}^2 (2.9)
Since this is a shared junction, in a SPICE simulation we would use
A_s=A_d=\lambda W=0.4 \mu \mathrm{m}^2 (2.10)
for each of the two transistors, which is much less than 2 \mu \mathrm{m}^2. The reduction in the perimeter is even more substantial. Here we have
P_{\mathrm{J} 3}=4 \lambda=0.8 \mu \mathrm{m} (2.11)
for the shared junction; so sharing this perimeter value over the two transistors would result in
P_s=P_d=2 \lambda=0.4 \mu \mathrm{m} (2.12)
for the appropriate junction of each transistor when simulating it in SPICE. This result is much less than the 4-μm perimeter for nodeJ_1 .