Collector characteristics for the Ge transistor of Fig. 3-15 are given in Fig. 3-16. If V_{EE} = 2 \text{V}, V_{CC} = 12 \text{V}, and R_C = 2 kΩ, size R_E so that V_{CEQ} = -6.4 \text{V}.
We construct, on Fig. 3-16, a dc load line having v_{CB} intercept -V_{CC} = -12 \text{V} and i_C intercept V_{CC}/R_C = 6 \text{mA}. The abscissa of the Q point is given by KVL around the transistor terminals:
V_{CBQ} = V_{CEQ} – V_{BEQ} = -6.4 – (-0.3) = -6.1 \text{V}
With the Q point defined, we read I_{EQ} = 3 \text{mA} from the graph. Now KVL around the emitter base loop leads to
R_{E} = \frac{V_{EE} + V_{BEQ}}{I_{EQ}} = \frac{2 + (-0.3)}{3 × 10^{-3}} = 566.7 Ω