Question 2.3: Consider a NMOS transistor biased with VGS = 0.65 V and with......
Consider a NMOS transistor biased with \mathrm{V}_{\mathrm{GS}}=0.65 \mathrm{~V} and with the device parameters listed for the 0.18-μm CMOS process in Table 1.5. How much does the drain current change with a 100 mV increase in V_{t n} , 5% decrease in C_{o x}, and 10% decrease in \mu_n?
| Table 1.5 MOSFET parameters repre sentative of v arious C MOS t echnologies and used for rough hand calculations in this text. | ||||||||
| 0.8 μm | 0.35 μm | 0.18 μm | 45 nm | |||||
| Technology | NMOS | PMOS | NMOS | PMOS | NMOS | PMOS | NMOS | PMOS |
| \mu \mathrm{C}_{\mathrm{ox}}\left(\mu \mathrm{A} / \mathrm{V}^2\right) | 92 | 30 | 190 | 55 | 270 | 70 | 280 | 70 |
| \mathrm{V}_{\mathrm{t} 0}(\mathrm{~V}) | 0.80 | -0.90 | 0.57 | -0.71 | 0.45 | -0.45 | 0.45 | -0.45 |
| \lambda \cdot \mathrm{L}(\mu \mathrm{m} / \mathrm{V}) | 0.12 | 0.08 | 0.16 | 0.16 | 0.08 | 0.08 | 0.10 | 0.15 |
| \mathrm{C}_{\mathrm{ox}}\left(\mathrm{fF} / \mu \mathrm{m}^2\right) | 1.8 | 1.8 | 4.5 | 4.5 | 8.5 | 8.5 | 25 | 25 |
| \mathrm{t}_{\mathrm{ox}}(\mathrm{nm}) | 18 | 18 | 8 | 8 | 5 | 5 | 1.2 | 1.2 |
| n | 1.5 | 1.5 | 1.8 | 1.7 | 1.6 | 1.7 | 1.85 | 1.85 |
| \theta(1 / \mathrm{V}) | 0.06 | 0.135 | 1.5 | 1.0 | 1.7 | 1.0 | 2.3 | 2.0 |
| m | 1.0 | 1.0 | 1.8 | 1.8 | 1.6 | 2.4 | 3.0 | 3.0 |
| \mathrm{C}_{\mathrm{ov}} / \mathrm{W}=\mathrm{L}_{\mathrm{ov}} \mathrm{C}_{\mathrm{ox}} (\mathrm{fF} / \mu \mathrm{m}) | 0.20 | 0.20 | 0.20 | 0.20 | 0.35 | 0.35 | 0.50 | 0.50 |
| \mathrm{C}_{\mathrm{db}} / \mathrm{W} \approx \mathrm{C}_{\mathrm{sb}} / \mathrm{W} (\mathrm{fF} / \mu \mathrm{m}) | 0.50 | 0.80 | 0.75 | 1.10 | 0.50 | 0.55 | 0.45 | 0.50 |
Note that since Table 1.5 indicates a threshold voltage of \mathrm{V}_{\mathrm{tn}}=0.45 \mathrm{~V}, \mathrm{a} \mathrm{V}_{\mathrm{t}} increase of 100 mV represents a 50% decrease in \mathrm{V}_{\mathrm{eff}},\text { from } 200 \mathrm{mV} \text { to } 100 \mathrm{mV} \text {. } Adopting a simple square law device model, a great simplification considering the large process variations present on λ, the nominal device drain current is given by
\mathrm{I}_{\mathrm{D}}=\frac{1}{2} \mu_{\mathrm{n}} \mathrm{C}_{\mathrm{ox}} \frac{\mathrm{W}}{\mathrm{L}} \mathrm{V}_{\mathrm{eff}}^2
Accounting for all of the process variations, the new drain current will be
\mathrm{I}_{\mathrm{D}, \mathrm{new}}=\frac{1}{2}\left(0.9 \mu_{\mathrm{n}}\right)\left(0.95 \mathrm{C}_{\mathrm{ox}}\right) \frac{\mathrm{W}}{\mathrm{L}}\left(0.5 \mathrm{~V}_{\mathrm{eff}}\right)^2=\left(0.9 \cdot 0.95 \cdot 0.5^2\right) \mathrm{I}_{\mathrm{D}}=0.214 \cdot \mathrm{I}_{\mathrm{D}}
representing a 79% decrease in drain current. Much of this is a result of the V_t variation.