Question 2.2: Consider the transistor shown in Fig. 2.18, where the total ......
Consider the transistor shown in Fig. 2.18, where the total width of the four parallel transistors is 80λ, its length is 2λ, and λ = 0.2 μm. Assuming node 2 is the source, node 1 is the drain, and the device is in the active region, find the source-bulk and drain-bulk capacitances given the parameters C_j=0.24 \mathrm{fF} / \mu \mathrm{m}^2 \text { and } C_{j-\mathrm{sw}}=0.2 \mathrm{fF} / \mu \mathrm{m}. Also find the equivalent capacitances if the transistor were realized as a single device with source and drain contacts still evenly placed.
Starting with node 1, the drain, we find that the areas of the junctions are equal to
\mathrm{A}_{\mathrm{J} 2}=\mathrm{A}_{\mathrm{J} 4}=6 \lambda \times 20 \lambda=120 \lambda^2=4.8 \mu \mathrm{m}^2
Ignoring the gate side, the perimeters are given by
\mathrm{P}_{\mathrm{J} 2}=\mathrm{P}_{\mathrm{J} 4}=6 \lambda+6 \lambda=12 \lambda=2.4 \mu \mathrm{m}
As a result, \mathrm{C}_{\mathrm{db}} can be estimated to be
\mathrm{C}_{\mathrm{db}}=2\left(\mathrm{~A}_{\mathrm{J} 2} \mathrm{C}_{\mathrm{j}}+\mathrm{P}_{\mathrm{J} 2} \mathrm{C}_{\mathrm{j}-\mathrm{sw}}\right)=3.3 \mathrm{fF}
For node 2, the source, we have
\mathrm{A}_{\mathrm{J} 1}=\mathrm{A}_{\mathrm{J} 5}=5 \lambda \times 20 \lambda=100 \lambda^2=4 \mu \mathrm{m}^2
and
\mathrm{A}_{\mathrm{J} 3}=\mathrm{A}_{\mathrm{J} 2}=4.8 \mu \mathrm{m}^2
The perimeters are found to be
\mathrm{P}_{\mathrm{J} 1}=\mathrm{P}_{\mathrm{J} 5}=5 \lambda+5 \lambda+20 \lambda=30 \lambda=6 \mu \mathrm{m}
and
P_{\mathrm{J} 3}=P_{\mathrm{J} 2}=2.4 \mu \mathrm{m}
resulting in an estimate for \mathrm{C}_{\mathrm{sb}} of
C_{s b}=\left(A_{J 1}+A_{J 3}+A_{J 5}+W L\right) C_j+\left(P_{J 1}+P_{J 3}+P_{J 5}\right) C_{j-s w}
=\left(19.2 \mu \mathrm{m}^2\right) 0.24 \mathrm{fF} / \mu \mathrm{m}^2+(14.4 \mu \mathrm{m}) 0.2 \mathrm{fF} / \mu \mathrm{m}
=7.5 \mathrm{fF}
It should be noted that, even without the additional capacitance due to the WL gate area, node 1 has less capacitance than node 2 since it has less area and perimeter.
In the case where the transistor is a single wide device, rather than four transistors in parallel, we find
A_J=5 \lambda \times 80 \lambda=400 \lambda^2=16 \mu \mathrm{m}^2
and
P_{\mathrm{J}}=5 \lambda+5 \lambda+80 \lambda=90 \lambda=18 \mu \mathrm{m}
resulting in \mathrm{C}_{\mathrm{db}}=7.4 \mathrm{fF} \text { and } \mathrm{C}_{\mathrm{sb}}=9.0 \mathrm{fF} \text {. } Note that in this case, C_{\mathrm{db}} is nearly twice what it is when four parallel transistors are used.