Find the value of the emitter resistor RE that, when added to the Si transistor circuit of Fig. 3-17, would bias for operation about VCEQ=5 V. Let ICEO=0, β=80, RF=220 kΩ, RC=2 kΩ, and VCC=12 V.
Application of KVL around the transistor terminals yields
IBQ=RFVCEQ – VBEQ=220 × 1035 – 0.7=19.545 μA
Since leakage current is zero, (3.1) and (3.2) give IEQ=(β+1)ICQ; thus KVL around the collector circuit gives
α(≡hFB)≡IEIC – ICBO (3.1)
β(≡hFE)≡1 – αα≡IBIC – ICEO (3.2)
(IBQ+βIBQ)RC+(β+1)IBQRE=VCC – VCEQ
so RE=(β+1)IBQVCC – VCEQ – (β+1)IBQRC=(80 + 1)(19.545 × 10−6)12 – 5 – (80 + 1)(19.545 × 10−6)(2 × 103)=2.42 kΩ