The differential amplifier of Fig. 4-22 includes identical JFETs with I_{DSS} = 10 \text{mA} and V_{p0} = 4 \text{V}. Let V_{DD} = 15 \text{V}, V_{SS} = 5 \text{V}, and R_S = 3 kΩ. If the JFETs are described by (4.2), find the value of R_D required to bias the amplifier such that V_{DSQ1} = V_{DSQ2} = 7 \text{V}.
i_D = I_{DSS} \left( 1 + \frac{v_{GS}}{V_{p0}} \right)^2 (4.2)
By symmetry, I_{DQ1} = I_{DQ2}. KCL at the source node requires that
I_{SQ} = I_{DQ1} + I_{DQ2} = 2I_{DQ1} (1)
With i_{G1} = 0, KVL around the left gate-source loop gives
V_{GSQ1} = V_{SS} – I_{SQ}R_S = V_{SS} – 2I_{DQ1}R_S (2)
Solving (4.2) for V_{GSQ} and equating the result to the right side of (2) gives
V_{p0} \left[ \left( \frac{I_{DQ1}}{I_{DSS}} \right)^{1/2} – 1 \right] = V_{SS} – 2I_{DQ1}R_S (3)
Rearranging (3) results in a quadratic in I_{DQ}:
I^2_{DQ1} – \left[\frac{V_{SS} + V_{p0}}{R_S} + \left( \frac{V_{p0}}{2R_S}\right)^2 \frac{1}{I_{DSS}} \right]I_{DQ1} + \left(\frac{V_{SS} + V_{p0}}{2R_S} \right)^2 = 0 (4)
Substituting known values into (4) yields
I^2_{DQ1} – 3.04 × 10^{-3} I_{DQ1} + 2.25 × 10^{-6} = 0 (5)
Applying the quadratic formula to (5) and disregarding the extraneous root yields I_{DQ1} = 1.27 \text{mA}.
Now the use of KVL around the left drain-source loop gives
V_{DD} + V_{SS} – V_{DSQ1} = I_{DQ1}R_D + I_{SQ}R_S (6)
Substituting (1) into (6) and solving the result for R_D leads to the desired result:
R_D = \frac{V_{DD} + V_{SS} – V_{DSQ1} – 2I_{DQ1}R_S}{I_{DQ1}} = \frac{15 + 5 – 7 – 2(1.27 × 10^{-3})(3 × 10^{3})}{1.27 × 10^{-3} } = 4.20 kΩ