A 5-μm/40-nm MOSFET biased at 1 mA exhibits a transconductance of 1/(100 Ω). If the sheet resistance of the gate polysilicon is equal to 30 Ω/, what is the widest finger that the structure can incorporate while ensuring that the gate thermal noise voltage is one-fifth of the gate-referred channel

Question

A 5-μm/40-nm MOSFET biased at 1 mA exhibits a transconductance of 1/(100 Ω). If the sheet resistance of the gate polysilicon is equal to 30 Ω/[latex]\square [/latex], what is the widest finger that the structure can incorporate while ensuring that the gate thermal noise voltage is one-fifth of the gate-referred channel thermal noise voltage?

Accepted Answer

If the transistor is laid out as N parallel fingers, each finger exhibits a distributed resistance of 30 Ω × (5/0.04)/N. Using the gate-referred channel thermal noise from Chapter 7, we have for the overall transistor

[latex] \begin{aligned} ext { Channel Noise } &=\sqrt{4 k T \gamma(100)} V / \sqrt{ Hz } &(19.1)\ ext { Gate Noise } &=\sqrt{4 k T \frac{150}{0.04 N^2} \frac{1}{3}} V / \sqrt{ Hz }&(19.2) \end{aligned} [/latex]

where the factor 1/3 on the right-hand side of (19.2) accounts for the distributed nature of the resistance (Chapter 7). Equating (19.1) to five times (19.2) and assuming that γ = 1, we have

N = 17.7 (19.3)

Thus, a minimum of 18 fingers is required.

Question 19.1: A 5-μm/40-nm MOSFET biased at 1 mA exhibits a transconductan...

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