Question 3.2: A transimpedance amplifier will be designed with a low-frequ...
A transimpedance amplifier will be designed with a low-frequency “gain” of 2000 ohm (66 dBΩ), flat up to 1 GHz, delivering a rail-to rail output voltage swing to a C_L= 1 pF external capacitive load.
The internal impedance of the driving current signal source is 10 k ohm parallel to 50 fF (the output impedance of the previous stage).
The design will be made using the AMS 0.35 micron CMOS technology parameters.
As one of the candidate configurations, we will design a CMOS inverter type circuit.
Since any peaking on the frequency response (any over-shoot on the pulse response) is not acceptable, a double-pole solution is targeted.
The design will be made using the expressions derived in this section, and then fine-tuned with PSpice.
The circuit diagram is as shown in Fig. 3.25.
The input capacitance (C_i) in the expressions is the sum of the signal source internal capacitance (which is given as 50 fF) and the gate–source capacitances of the transistors (which are not known yet).
Similarly, the output capacitance (C_o) is the sum of the load capacitance (which is given as 1 pF) and the junction capacitances of the transistors (which are not known).
The only known component is G_F, which is approximately equal to 1/Z_m(0) =0.5 mS.
Another aspect that must be kept in mind is that the width of the PMOS transistor must be approximately (\mu_{no}/\mu_{po}) times bigger than that of the NMOS transistor (see Chapter 2).
This ratio is 475.8/137\cong 3.5 for AMS 0.35 micron CMOS technology (see Appendix A).
For maximum high-frequency performance, the gate lengths of both transistors will
be chosen as 0.35 μm.
To estimate the dimensions of the transistors, expressions (3.46) and (3.47) can be
used.
If we insert (3.46) into (3.47) and make some simplifications assuming that
C_F\lt C_i and \bar{g_{ds}}\ll \bar{g_{m}} Z (both being realistic), we obtain
\omega_p\cong \frac{\bar{g_{ds}}}{2C_o}+\frac{G_F}{C_i} (3.48)
The bandwidth (3 dB frequency) was given as 1 GHz. Since the amplifier has a double-pole, the frequency corresponding to the pole is f_p =1 GHz/0.614 = 1.628 GHz, or \omega_p = 2\pi 1.628\times 10^9\cong 10^{10} rad/s.
But since all parameters – except G_F – are geometry dependent, (3.48) does not lead to the solution.
Another attack point is to consider the slew-rate.
The rise-time of a 1 GHz bandwidth amplifier is approximately t_r = 0.35/f_{3dB} = 0.35/10^9 = 0.35 ns (Chapter 2).
For a rail-to-rail output step, the PMOS transistor that acts as a current source must be
capable of charging the total load capacitance up to V_{DD}= 1.5 V in 0.35 ns:
I_p=C_o\frac{dV}{dT}=C_o\frac{1.5}{0.35\times 10^{-9}} (3.49)
C_o is the sum of the external load capacitance (1 pF) and the total parasitic capacitance of the output node.
This parasitic capacitance can be calculated (see Appendix 1) in terms of the widths of the transistors as
C_{jDN}(0)=0.8W_N+0.5(X+W_N)\cong 1.3 W_N[fF,W_N in μm]
C_{jDP}(0)=0.8W_P+0.5(X+W_P)\cong 1.3 W_P[fF,W_N in μm]
and the total parasitic capacitance{}^7
C_{jDT}(0)=\cong 1.3(W_N+W_P)=1.3(1+3.5)W_N=5.85 W_N[fF,W_N in μm]
