A transimpedance amplifier will be designed with a low-frequency “gain” of 2000 ohm (66 dBΩ), flat up to 1 GHz, delivering a rail-to rail output voltage swing to a CL= 1 pF external capacitive load. The internal impedance of the driving current signal source is 10 k ohm parallel to 50 fF

Question

A transimpedance amplifier will be designed with a low-frequency “gain” of 2000 ohm (66 dBΩ), flat up to 1 GHz, delivering a rail-to rail output voltage swing to a [latex]C_L[/latex]= 1 pF external capacitive load.

The internal impedance of the driving current signal source is 10 k ohm parallel to 50 fF (the output impedance of the previous stage).

The design will be made using the AMS 0.35 micron CMOS technology parameters.

As one of the candidate configurations, we will design a CMOS inverter type circuit.

Since any peaking on the frequency response (any over-shoot on the pulse response) is not acceptable, a double-pole solution is targeted.

The design will be made using the expressions derived in this section, and then fine-tuned with PSpice.

Accepted Answer

The circuit diagram is as shown in Fig. 3.25.

The input capacitance [latex](C_i)[/latex] in the expressions is the sum of the signal source internal capacitance (which is given as 50 fF) and the gate–source capacitances of the transistors (which are not known yet).
Similarly, the output capacitance [latex](C_o)[/latex] is the sum of the load capacitance (which is given as 1 pF) and the junction capacitances of the transistors (which are not known).
The only known component is [latex]G_F[/latex], which is approximately equal to [latex]1/Z_m(0) =0.5 mS[/latex].

Another aspect that must be kept in mind is that the width of the PMOS transistor must be approximately [latex](\mu_{no}/\mu_{po})[/latex] times bigger than that of the NMOS transistor (see Chapter 2).

This ratio is [latex]475.8/137\cong 3.5[/latex] for AMS 0.35 micron CMOS technology (see Appendix A).
For maximum high-frequency performance, the gate lengths of both transistors will
be chosen as 0.35 μm.

To estimate the dimensions of the transistors, expressions (3.46) and (3.47) can be
used.

If we insert (3.46) into (3.47) and make some simplifications assuming that
[latex]C_F\lt C_i[/latex] and [latex]\bar{g_{ds}}\ll \bar{g_{m}} Z[/latex] (both being realistic), we obtain

[latex]\omega_p\cong \frac{\bar{g_{ds}}}{2C_o}+\frac{G_F}{C_i}[/latex] (3.48)

The bandwidth (3 dB frequency) was given as 1 GHz. Since the amplifier has a double-pole, the frequency corresponding to the pole is [latex]f_p [/latex]=1 GHz/0.614 = 1.628 GHz, or [latex]\omega_p = 2\pi 1.628 imes 10^9\cong 10^{10}[/latex] rad/s.

But since all parameters – except [latex]G_F[/latex] – are geometry dependent, (3.48) does not lead to the solution.
Another attack point is to consider the slew-rate.

The rise-time of a 1 GHz bandwidth amplifier is approximately [latex]t_r = 0.35/f_{3dB} = 0.35/10^9 = 0.35[/latex] ns (Chapter 2).

For a rail-to-rail output step, the PMOS transistor that acts as a current source must be
capable of charging the total load capacitance up to [latex]V_{DD}= 1.5 V[/latex] in 0.35 ns:

[latex]I_p=C_o\frac{dV}{dT}=C_o\frac{1.5}{0.35 imes 10^{-9}}[/latex] (3.49)

[latex]C_o[/latex] is the sum of the external load capacitance (1 pF) and the total parasitic capacitance of the output node.

This parasitic capacitance can be calculated (see Appendix 1) in terms of the widths of the transistors as

[latex]C_{jDN}(0)=0.8W_N+0.5(X+W_N)\cong 1.3 W_N[/latex][fF,[latex]W_N[/latex] in μm]

[latex]C_{jDP}(0)=0.8W_P+0.5(X+W_P)\cong 1.3 W_P[/latex][fF,[latex]W_N[/latex] in μm]

and the total parasitic capacitance[latex]{}^7[/latex]

[latex]C_{jDT}(0)=\cong 1.3(W_N+W_P)=1.3(1+3.5)W_N=5.85 W_N[/latex][fF,[latex]W_N[/latex] in μm]

Question 3.2: A transimpedance amplifier will be designed with a low-frequ...

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