Compare the design of PMOS only to a complementary VCO topology. Design each for best swing to achieve the lowest phase noise. The VCOs should oscillate at 5 GHz in a 0.18-μm CMOS technology. A 1-nH inductor with a Q of 10 is available for the design. Assume for this design that the mobility of

Question

Compare the design of PMOS only to a complementary VCO topology. Design each for best swing to achieve the lowest phase noise. The VCOs should oscillate at 5 GHz in a 0.18- [latex]\mu [/latex] m CMOS technology. A 1-nH inductor with a [latex] Q [/latex] of 10 is available for the design. Assume for this design that the mobility of the PMOS transistors is one-third that of the NMOS transistors and design the VCOs to be powered from a 1.5-V supply.

Accepted Answer

A 1-nH inductor with a Q of 10 will have 314 [latex]\Omega [/latex] of parallel resistance. To get the VCO to oscillate at 5 GHz with a 1- nH inductor will mean that the total capacitance due to the transistors, plus additional capacitance, should be about 1 pF. Now the VCO current must be set appropriately. With the complementary design, the voltage at the resonator will swing about mid-rail to the supply and down to ground, leaving some room for the current source to operate correctly. If the current source can be operated with 300 mV of headroom, this will mean that the maximum peak-to-peak swing for this design will be 1.2V. The current should be set to give this amplitude for lowest phase noise, but more current will be wasted and lead to excess noise. Therefore, for the complementary design, the current should be set so that the peak voltage swing is 0.6V. Therefore,

[latex]I_{ ext {comp }}=\frac{2 R_{P} I}{\left.\pi \cdot v_{ ext {out }} ight|_{ ext {Comp }}}=3 mA[/latex]

In the case of the PMOS design, leaving 300 mV for the current source, the peak swing should be 1.2V. Therefore, the current should be set to

[latex]\left.I_{ PMOS } v_{ ext {out }} ight|_{S E}=\frac{R_{P} I}{\left.\pi \cdot v_{ ext {out }} ight|_{ ext {PMOS }}}=12 mA [/latex]

Now with twice the swing but exactly the same resistance and Q, theoretically the phase noise of the PMOS design should be 6 dB better than the phase noise of the complementary design, but at the cost of four times the power. If the PMOS design were chosen to have the same swing as the complementary design, then it would draw 6 mA of current, thus delivering the same phase noise as the complementary design but at twice the power.
In order for these designs to be built, the transistors must be sized. For the complementary design, the PMOS transistors are chosen to have a length of 0.18 [latex]\mu [/latex] m and the NMOS transistors to have a length of

[latex]L_{n} = L_{P} \sqrt{\frac{\mu n}{\mu p} } = 0.31\mu m [/latex]

The widths of the transistors must be set large enough that 1/f noise is not too large and the on resistance of the devices does not act to limit the swing excessively, but not so large that the parasitic capacitance of the devices dominates the frequency of oscillation. In this design, the width of the NMOS was chosen to be 55 [latex]\mu [/latex] m, while the PMOS width was set to be 110 [latex]\mu [/latex] m (note that this is a ratio of 2:1, which is different from theory, in order to get both the [latex]C_{gs} [/latex] and the [latex]g_{m} [/latex] to match closely in simulation). In the case of the PMOS-only design, the transistors were made wider (175 [latex]\mu [/latex] m) in order to accommodate the larger currents. The singleended output voltage for each of the designs is shown in Figure 8.37. This shows that the designs have close to the predicted output swings. The PMOS design with 12 mA is a little lower due to the finite source-drain resistance of the PMOS at higher currents.

The phase noise for the three designs is shown in Figure 8.38. As predicted, the phase noises of the PMOS VCO and the complementary VCO are identical when they have the same output swing, although the PMOS VCO burns twice as much current. When the PMOS design is run at full swing, it delivers 4 to 5 dB better phase noise then the complementary design is capable of delivering. Note that this is slightly less than the 6 dB that simple theory would predict because more current means that more noise is produced in this design.

Question 8.4: Compare the design of PMOS only to a complementary VCO topol...

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