Integrated Circuit Design for High-Speed Frequency Synthesis by John Rogers, Calvin Plett, Foster Dai | 9781580539821 | 1580539823 | Holooly

Electric Circuits

Integrated Circuit Design for High-Speed Frequency Synthesis

32 SOLVED PROBLEMS

Question: A.4

A continuous-time signal (a square wave) is given by fstep (t) = u(t − T) − u(t − 3T) − [u(t − 5T) − u(t − 7T)] This signal is applied to a system with a transfer function given by \frac{vout}{vin } = \frac{1}{1-z-1 } Determine the time domain output of the system. ...

Verified Answer:

First, we take the transfer function and cross-mul...

Question: A.5

Plot the root locus for the variable K in the following open-loop gain transfer function: F(s) = K s .(s + 4) . (s + 5)/(s + 1)(s + 6)(s + 7)(s + 1 + j)(s + 1 − j)} ...

Verified Answer:

The root locus for this system begins with the ope...

Question: 9.1

Let us assume that we are sampling a 4-kHz voice signal with an 8-bit video A/D at 8 MHz. Determine the oversampling ratio and the improvement in SNR. ...

Verified Answer:

The Nyquist rate is 8 kHz; thus, the oversampling ...

Question: 8.6

Design a quadrature oscillator oscillating at 2 GHz. Phase noise should be better than −100 dBc/Hz at a 1-MHz offset. Explore the quality of the quadrature phase matching with an output load of 2 kV and a capacitor mismatch on one of the stages. ...

Verified Answer:

The technique is similar to the previous example, ...

Question: 8.5

Design a single-ended ring oscillator operating at 1 GHz with phase noise of −100 dBc/Hz at a 1-MHz offset. ...

Verified Answer:

In a 0.13-

\mu

m process, the power ...

Question: 8.4

Compare the design of PMOS only to a complementary VCO topology. Design each for best swing to achieve the lowest phase noise. The VCOs should oscillate at 5 GHz in a 0.18-μm CMOS technology. A 1-nH inductor with a Q of 10 is available for the design. Assume for this design that the mobility of ...

Verified Answer:

A 1-nH inductor with a Q of 10 will have 314 [late...

Question: 9.2

Compare the fractional accumulator output (m = 1) to the third-order ∑D modulator output (m = 3) for the case of N(z) = I(z) +. F(z) = 100 + 1/32, with a reference frequency of fr = 10 MHz. ...

Verified Answer:

The simulated accumulator outputs are given in Fig...

Question: 9.3

Consider the synthesizer originally designed in Examples 3.4 and 3.5. If the fractional-N design is to be controlled by a MASH ∑D modulator, find the minimum order of the MASH ∑D modulator such that the phase noise performance of the design will not be compromised. ...

Verified Answer:

First, recall that the reference frequency of the ...

Question: 10.2

Design the current sources for a sine-weighted nonlinear DAC with 8-bit phase and 8-bit amplitude resolution. ...

Verified Answer:

For 8-bit phase resolution, W = 8. The two MSBs ar...

Question: A.1

Illustrate the use of the preceding equations to take a time domain waveform and transform it to the z domain. ...

Verified Answer:

For example, the unit step function u(t) can be tr...

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