Question 18.1: Consider the multiply-by-two amplifier of Sec. 13.3.3, shown...
Consider the multiply-by-two amplifier of Sec. 13.3.3, shown in Fig. 18.18(a) as an implementation using a MOS capacitor C_1 and a linear capacitor C_2 . Explain how the output voltage in the amplification mode is distorted.
Suppose for simplicity that V_{i n} is below ground by more than V_{T H}, so that the NMOS capacitors are in strong inversion during sampling. As the circuit enters the amplification mode, the voltage across C_1 approaches zero and the total charge stored on C_1 is transferred to C_2. How much is this charge? If C_1 were linear, we would have Q=C_1 V, but here we must write d Q=C_1 d V. Thus, as shown in Fig. 18.18(b), the total transferred charge when the voltage across the capacitor goes from V_{\text {in }} to zero is equal to the area under the C/V characteristic, a value substantially less than that in the linear case. The output voltage is then given by
V_{o u t} \approx V_{i n}+\frac{1}{C_2} \int_0^{V_{i n}} C_1 d V (18.1)