Create the machine code equivalent of the following assembly language program.

Question

andi $3, $3, 0 ; initialize loop counter $3 to 0

andi $2, $2, 0 ; clear register for loop bound
addi $2, $2, 4000 ; loop bound register

$label: 1w $15, 4000($3) ; load x(i) to R15

lw $14, 8000($3) ; load y(i) to R14

add $24, $15, $14 ; x(i) + y(i)

sw $24, 8000($3) ; save new y(i)

addi $3, $3, 4 ; update address register, address= address + 4

bne $3, $2, $label

Accepted Answer

The first instruction

andi $3, $3, 0

can be translated as follows. Table 9-7 shows that the opcode for andi is 12. Hence, the first 6 bits for the first instruction will be 001100 as indicated in row 1 (after the header row) of Table 9-8. The source register field is next. It should be 00011, because the source register is $3. The destination register field is next. It should be 00011, because the destination register is $3. The immediate constant is 0, and it leads to sixteen 0s in bits 0 to 15. This explains the contents of row 1. In hex representation, it becomes 3063 0000.

			Fields
Name	Format	Bits 31..26	Bits 25..21	Bits 20-16	Bits 15-11	Bits 10-6	Bits 5..0	Instruction (operation dest, src1, src2)
Add	R	0	2	3	1	0	32	add $1,$2, $s3
Sub	R	0	2	3	1	0	34	sub $1, $2, $3
addi	I	8	2	1	100			addi $1, $2, 100
addu	R	0	2	3	1	0	33	addu $1, $2, $3
subu	R	0	2	3	1	0	35	subu $1, $2, $3
addiu	I	9	2	1	100			addiu $1,$2, 100
mfc0	R	16	0	1	14	0	0	mfc0 $1, $epc
mult	R	0	2	3	0	0	24	mult $2, $3
multu	R	0	2	3	0	0	25	multu $2, $3
div	R	0	2	3	0	0	26	div $2, $3
divu	R	0	2	3	0	0	27	divu $2, $3
mfhi	R	0	0	0	1	0	16	mfhi $1
mflo	R	0	0	0	1	0	18	mflo $1
and	R	0	2	3	1	0	36	and $1, $2, $3
or	R	0	22	3	1	0	37	or $1,$2, $3
andi	I	12	2	1	100			andi $1, $2, 100
ori	I	13	2	1	100			ori $1, $2, 100
sll	R	0	0	2	1	10	0	sll $1, $2, 10
srl	R	0	0	2	1	10	2	srl $1, $2, 10
lw	I	35	2	1	100			lw $1, 100($2)
sw	I	43	2	1	100			sw $1, 100($2)
lui	I	15	0	1	100			lui $1, 100
beq	I	4	1	2	25			beq $1, $2, 100
bne	I	5	1	2	25			bne $1, $2, 100
slt	R	0	2	3	1	0	42	slt $1, $2, $3
slti	I	10	2	1	100			slti $1, $2, 100
sltu	R	0	22	3	1	0	43	sltu $1, $2, $3
sltiu	I	11	2	1	100			sltiu $1, $2, 100
j	J	2	2500					j 10000
jr	R	0	31	0	0	0	8	jr $31
jal	J	3	2500					jal 10000

We will also explain the encoding of the last instruction, bne $3, $2, label. The opcode is 5 (i.e., 000101). The next field corresponds to register $3, so it is 00011. The next field is 00010 to indicate the register $2. The byte offset should be 224, but the instruction is supposed to contain the word offset, which is 224 divided by 4 (i.e., 26). In 2’s complement representation, it is 1010. Sign extending to fill the sixteen bits, one gets 1111111111111010, which will occupy bits 0 to 15. Machine code corresponding to all the instructions is shown in Table 9-8.

Table 9-8: MIPS Machine Code for Example 2; Binary as Well as Hex Representations Are Shown
Instruction	Bits	Bits	Bits	Bits	Bits	Bits	Equivalent Hex
Instruction	31–26	25–21	20–16	15–11	10–6	5–0	Equivalent Hex
andi $3, $3, 0	001100	00011	00011	00000	00000	000000	3063 0000
andi $2, $2, 0	001100	00010	00010	00000	00000	000000	3042 0000
addi $2, $2, 4000	001000	00010	00010	00001	11110	100000	2042 0FA0
lw $15, 4000($3)	100011	00011	01111	00001	11110	100000	8C6F 0FA0
lw $14, 8000($3)	100011	00011	01110	00011	11101	000000	8C6E 1F40
add $24, $15, $14	000000	01111	01110	11000	00000	100000	01EE C020
sw $24, 8000($3)	101011	00011	11000	00011	11101	000000	B478 1F40
addi $3, $3, 4	001000	00011	00011	00000	00000	000100	2063 0004
bne $3, $2, –6	000101	00011	00010	11111	11111	111010	1462 FFA

Question 9.2: Create the machine code equivalent of the following assembly...

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