Digital Systems Design Using Verilog 1st. Edition by Charles Roth, Lizy K. John, Byeong Kil Lee | 9781285051079 | 1285051076 | Holooly

Digital Systems Design

Digital Systems Design Using Verilog

21 SOLVED PROBLEMS

Question: 3.2

Implement, in ROM, a sequential machine whose state table is given in Figure 3-7: You may note that this is the BCD to Excess-3 code converter that we designed in Chapter 1. ...

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A sequential circuit can easily be designed using ...

Question: 9.2

Create the machine code equivalent of the following assembly language program. ...

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The first instruction andi $3, ...

Question: 4.2

Is ripple-carry adder the smallest 32-bit adder? ...

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A 32-bit ripple-carry adder uses 32 1-bit adders. ...

Question: 2.5

Parity bits are often used in digital communication for error detection and correction. The simplest of these involve transmitting one additional bit with the data, a parity bit. Use Verilog arrays to represent a parity generator that generates a 5-bit-odd-parity generation for a 4-bit input number ...

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The input word is a 4-bit binary number. A 5-bit o...

Question: 2.4

What is the hardware obtained if the following code is synthesized? Note that this is the same code as in the previous example, but with the statement order inside the always block reversed. ...

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A single flip-flop Explanation: The list of sta...

Question: 2.3

What is the hardware obtained if the following code is synthesized? ...

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A 3-bit shift register Explanation: The list of...

Question: 2.2

What is wrong with the following code for a half adder that must add if add signal equals 1? always @(*) begin if (add == 1) sum = x ^ y; carry = x & y; else sum = 0; carry = 0; end (a) It will compile but not simulate correctly (b) It will compile and simulate correctly but not ...

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(d). This code will not even compile due to the mi...

Question: 2.1

For a half adder, sum and carry can be found using the equations sum = x XOR y ; carry = x AND y. What is wrong with the following code for a half adder that must add if add signal equals 1? always @(*) begin if (add == 1) sum = x ^ y; carry= x & y; end (a)It will compile but not simulate correctly ...

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(a). This code will compile but will not simulate ...

Question: 1.2

Consider the circuit in Figure 1‐43 with the following minimum/maximum delays: CLK‐to‐Q for flip‐flop A: 7ns/9ns CLK‐to‐Q for flip‐flop B: 8ns/10ns CLK‐to‐Q for flip‐flop C: 9ns/11ns Combinational logic: 3ns/4ns Setup time for flip‐flops: 2ns Hold time for flip‐flops: 1ns Compute the delays for all ...

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Remember that a timing path starts at either a pri...

Question: 1.3

Consider the circuit in Figure 1‐35 with the following minimum/maximum delays: CLK‐to‐Q for flip‐flop 1: 5ns/8ns CLK‐to‐Q for flip‐flop 2: 7ns/9ns XOR Gate: 4ns/6ns AND Gate: 1ns/3ns Setup time for flip‐flops: 5ns Hold time for flip‐flops: 2ns (a) What is the minimum clock period that this circuit ...

Verified Answer:

(a): Since XOR gate delay is higher than the AND g...

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