Question 8.27: Figure 8.59 (a) shows a preliminary design for a two-stage a...
Figure 8.59 (a) shows a preliminary design for a two-stage amplifier that will drive a resistive load RL=2 kΩ. The available input voltage is νS=VScos(2πf0t), with VS≤10 mV and f0≥50 Hz. The source resistance RS is no larger than 50 Ω. For frequencies greater than or equal to f0, the minimum overall voltage gain is to be Aν=800, with about equal gain from each stage. The first stage is to be capacitively coupled to the second, as shown, in case imperfect cancellation of the input voltage offset in the first stage produces an undesirable dc component in the first-stage output ν1. The available power-supply voltages are ±VCC=±15 V. The power supply output resistance and associated wiring resistance is less than 2 Ω. Complete the design. Include bias-current compensation resistors.

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Figure 8.59 (b) shows a circuit diagram for the amplifier. The power-supply circuitry is omitted to avoid cluttering the diagram.
The voltage gain for frequencies much larger than 50 Hz is not specified, but we know it must be larger than 800 . The larger we make the overall high-frequency voltage gain, the smaller will be the parameter k in (8.69) and (consequently) the smaller will be the required coupling capacitance. The maximum allowable voltage gain is determined by the maximum amplitude of the input (10 mV) and the supply voltage (15 V) . Assuming railto-rail operation,
C≥ω0R1−k2k (8.69)
max(Aν)=10 mV15 V=1,500
To provide a little margin, we choose, somewhat arbitrarily,
Aν=352=1,225
It follows that
k=1,225800=0.653.
The feedback networks in the inverting and non-inverting amplifiers are the same, so that the voltage gains of the two stages are approximately the same and approximately equal to 35. We choose R2=1 MΩ to minimize the load on each op amp and to allow a large input resistance. Thus, for the inverting amplifier,
R1R2=35,R2=1MΩ⇒R1=35R2≅28.6 kΩ .
For the non-inverting amplifier,
1+R3R4=35,R4=1MΩ⇒R3=34R4=29.4 kΩ.
From (8.80) and (8.82) , the bias-current compensation resistances are
In(R2∥2Ri)=Ip(RX∥2Ri)⇒RX=R2 , (8.80)
RX=R1∥R2≅R1,R2≫R1 . (8.82)
RX=R2=1MΩ,RY=R3=29.4 kΩ.
The lowest frequency of interest is 50 Hz and the input resistance for the second stage is approximately RY. From (8.69), we require a coupling capacitance
C≥ω0R1−k2k . (8.69)
C=2πf0R31−k2k⇒C=93.4 nF
The more precise relation (8.70) gives
C≥2πf0RL1−k2k1−1−k2k2RLRS(2+RLRS)1 (8.70)
C=2πf0R31−k2k1−1−k2k2R3RS(2+R3RS)1=93.5 nF.
The difference, given typical tolerances on capacitors, is insignificant. Figure 8.60 below shows a simulation of the circuit. The measured voltage gain at 50 Hz is
Aν=9.998 mV7.999 V≅800.
