Question 8.27: Figure 8.59 (a) shows a preliminary design for a two-stage a...

Figure 8.59 (a) shows a preliminary design for a two-stage amplifier that will drive a resistive load RL=2  kΩR_L=2   \mathrm{k} \Omega. The available input voltage is νS=VScos(2πf0t)\nu_S=V_S \cos \left(2 \pi f_0 t\right), with VS10 mVV_S \leq 10  \mathrm{mV} and f050  Hzf_0 \geq 50  \mathrm{~Hz}. The source resistance RSR_S is no larger than 50 Ω50  \Omega. For frequencies greater than or equal to f0f_0, the minimum overall voltage gain is to be Aν=800A_\nu=800, with about equal gain from each stage. The first stage is to be capacitively coupled to the second, as shown, in case imperfect cancellation of the input voltage offset in the first stage produces an undesirable dc component in the first-stage output ν1\nu_1. The available power-supply voltages are ±VCC=±15  V\pm V_{C C}=\pm 15  \mathrm{~V}. The power supply output resistance and associated wiring resistance is less than 2  Ω2   \Omega. Complete the design. Include bias-current compensation resistors.

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Figure  8.59 (b) shows a circuit diagram for the amplifier. The power-supply circuitry is omitted to avoid cluttering the diagram.

The voltage gain for frequencies much larger than  50 Hz 50 \mathrm{~Hz}  is not specified, but we know it must be larger than 800 . The larger we make the overall high-frequency voltage gain, the smaller will be the parameter k in (8.69) and (consequently) the smaller will be the required coupling capacitance. The maximum allowable voltage gain is determined by the maximum amplitude of the input (10 mV) (10  \mathrm{mV})  and the supply voltage (15  V) (15  \mathrm{~V}) . Assuming railto-rail operation,

Ckω0R1k2 C \geq \frac{k}{\omega_0 R \sqrt{1-k^2}}        (8.69)

max(Aν)=15  V10 mV=1,500 \max \left(A_\nu\right)=\frac{15  \mathrm{~V}}{10  \mathrm{mV}}=1,500

To provide a little margin, we choose, somewhat arbitrarily,

Aν=352=1,225 A_\nu=35^2=1,225

It follows that

k=8001,225=0.653. k=\frac{800}{1,225}=0.653.

The feedback networks in the inverting and non-inverting amplifiers are the same, so that the voltage gains of the two stages are approximately the same and approximately equal to 35. We choose R2=1 MΩ R_2=1  \mathrm{M} \Omega to minimize the load on each op amp and to allow a large input resistance. Thus, for the inverting amplifier,

R2R1=35,R2=1MΩR1=R23528.6 kΩ \frac{R_2}{R_1}=35, R_2=1 \mathrm{M} \Omega \Rightarrow R_1=\frac{R_2}{35} \cong 28.6  \mathrm{k} \Omega .

For the non-inverting amplifier,

1+R4R3=35,R4=1MΩR3=R434=29.4 kΩ1+\frac{R_4}{R_3}=35, R_4=1 \mathrm{M} \Omega \Rightarrow R_3=\frac{R_4}{34}=29.4  \mathrm{k} \Omega.

From  (8.80)  and  (8.82) , the bias-current compensation resistances are

In(R2Ri2)=Ip(RXRi2)RX=R2 I_n\left(R_2 \| \frac{R_i}{2}\right)=I_p\left(R_X \| \frac{R_i}{2}\right) \Rightarrow R_X=R_2 ,    (8.80)

 

RX=R1R2R1,R2R1 R_X=R_1 \| R_2 \cong R_1, R_2 \gg R_1 .     (8.82)

 

 RX=R2=1MΩ,RY=R3=29.4 kΩ. R_X=R_2=1 \mathrm{M} \Omega, R_Y=R_3=29.4  \mathrm{k} \Omega .

 

The lowest frequency of interest is 50 Hz 50 \mathrm{~Hz}  and the input resistance for the second stage is approximately RY R_Y . From (8.69), we require a coupling capacitance

Ckω0R1k2 C \geq \frac{k}{\omega_0 R \sqrt{1-k^2}}   .  (8.69)

 

C=k2πf0R31k2C=93.4 nF C=\frac{k}{2 \pi f_0 R_3 \sqrt{1-k^2}} \Rightarrow C=93.4  \mathrm{nF}

The more precise relation (8.70) gives

Ck2πf0RL1k211k21k2RSRL(2+RSRL) C \geq \frac{k}{2 \pi f_0 R_L \sqrt{1-k^2}} \frac{1}{\sqrt{1-\frac{k^2}{1-k^2} \frac{R_S}{R_L}\left(2+\frac{R_S}{R_L}\right)}}         (8.70)

C=k2πf0R31k211k21k2RSR3(2+RSR3)=93.5 nF. \begin{aligned} C &=\frac{k}{2 \pi f_0 R_3 \sqrt{1-k^2}} \frac{1}{\sqrt{1-\frac{k^2}{1-k^2} \frac{R_S}{R_3}\left(2+\frac{R_S}{R_3}\right)}} \\\\ &=93.5  \mathrm{nF} . \end{aligned}

The difference, given typical tolerances on capacitors, is insignificant. Figure  8.60  below shows a simulation of the circuit. The measured voltage gain at 50  Hz 50  \mathrm{~Hz} is

Aν=7.999  V9.998 mV800. A_\nu=\frac{7.999  \mathrm{~V}}{9.998  \mathrm{mV}} \cong 800 .

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