Figure 8.59 (a) shows a preliminary design for a two-stage amplifier that will drive a resistive load RL=2kΩ. The available input voltage is νS=VScos(2πf0t), VS≤10 mV and f0≥50 Hz. The source resistance RS is no larger than 50Ω. For frequencies greater than or equal to f0, the minimum overall

Question

Figure 8.59 (a) shows a preliminary design for a two-stage amplifier that will drive a resistive load [latex]R_L=2 \mathrm{k} \Omega[/latex]. The available input voltage is [latex] u_S=V_S \cos \left(2 \pi f_0 t ight)[/latex], with [latex]V_S \leq 10 \mathrm{mV}[/latex] and [latex]f_0 \geq 50 \mathrm{~Hz}[/latex]. The source resistance [latex]R_S[/latex] is no larger than [latex]50 \Omega[/latex]. For frequencies greater than or equal to [latex]f_0[/latex], the minimum overall voltage gain is to be [latex]A_ u=800[/latex], with about equal gain from each stage. The first stage is to be capacitively coupled to the second, as shown, in case imperfect cancellation of the input voltage offset in the first stage produces an undesirable dc component in the first-stage output [latex] u_1[/latex]. The available power-supply voltages are [latex]\pm V_{C C}=\pm 15 \mathrm{~V}[/latex]. The power supply output resistance and associated wiring resistance is less than [latex]2 \Omega[/latex]. Complete the design. Include bias-current compensation resistors.

Accepted Answer

Figure 8.59 (b) shows a circuit diagram for the amplifier. The power-supply circuitry is omitted to avoid cluttering the diagram.

The voltage gain for frequencies much larger than [latex] 50 \mathrm{~Hz} [/latex] is not specified, but we know it must be larger than 800 . The larger we make the overall high-frequency voltage gain, the smaller will be the parameter k in (8.69) and (consequently) the smaller will be the required coupling capacitance. The maximum allowable voltage gain is determined by the maximum amplitude of the input [latex] (10 \mathrm{mV}) [/latex] and the supply voltage [latex] (15 \mathrm{~V}) [/latex] . Assuming railto-rail operation,

[latex] C \geq \frac{k}{\omega_0 R \sqrt{1-k^2}} [/latex] (8.69)

[latex] \max \left(A_ u ight)=\frac{15 \mathrm{~V}}{10 \mathrm{mV}}=1,500 [/latex]

To provide a little margin, we choose, somewhat arbitrarily,

[latex] A_ u=35^2=1,225 [/latex]

It follows that

[latex] k=\frac{800}{1,225}=0.653. [/latex]

The feedback networks in the inverting and non-inverting amplifiers are the same, so that the voltage gains of the two stages are approximately the same and approximately equal to 35. We choose [latex] R_2=1 \mathrm{M} \Omega [/latex] to minimize the load on each op amp and to allow a large input resistance. Thus, for the inverting amplifier,

[latex] \frac{R_2}{R_1}=35, R_2=1 \mathrm{M} \Omega \Rightarrow R_1=\frac{R_2}{35} \cong 28.6 \mathrm{k} \Omega[/latex] .

For the non-inverting amplifier,

[latex]1+\frac{R_4}{R_3}=35, R_4=1 \mathrm{M} \Omega \Rightarrow R_3=\frac{R_4}{34}=29.4 \mathrm{k} \Omega[/latex].

From (8.80) and (8.82) , the bias-current compensation resistances are

[latex] I_n\left(R_2 \| \frac{R_i}{2} ight)=I_p\left(R_X \| \frac{R_i}{2} ight) \Rightarrow R_X=R_2 [/latex] , (8.80)

[latex] R_X=R_1 \| R_2 \cong R_1, R_2 \gg R_1 [/latex] . (8.82)

[latex] R_X=R_2=1 \mathrm{M} \Omega, R_Y=R_3=29.4 \mathrm{k} \Omega . [/latex]

The lowest frequency of interest is [latex] 50 \mathrm{~Hz} [/latex] and the input resistance for the second stage is approximately [latex] R_Y [/latex]. From (8.69), we require a coupling capacitance

[latex] C \geq \frac{k}{\omega_0 R \sqrt{1-k^2}} [/latex] . (8.69)

[latex] C=\frac{k}{2 \pi f_0 R_3 \sqrt{1-k^2}} \Rightarrow C=93.4 \mathrm{nF} [/latex]

The more precise relation (8.70) gives

[latex] C \geq \frac{k}{2 \pi f_0 R_L \sqrt{1-k^2}} \frac{1}{\sqrt{1-\frac{k^2}{1-k^2} \frac{R_S}{R_L}\left(2+\frac{R_S}{R_L} ight)}} [/latex] (8.70)

[latex] \begin{aligned} C &=\frac{k}{2 \pi f_0 R_3 \sqrt{1-k^2}} \frac{1}{\sqrt{1-\frac{k^2}{1-k^2} \frac{R_S}{R_3}\left(2+\frac{R_S}{R_3} ight)}} \\ &=93.5 \mathrm{nF} . \end{aligned} [/latex]

The difference, given typical tolerances on capacitors, is insignificant. Figure 8.60 below shows a simulation of the circuit. The measured voltage gain at [latex] 50 \mathrm{~Hz} [/latex] is

[latex ] A_ u=\frac{7.999 \mathrm{~V}}{9.998 \mathrm{mV}} \cong 800 . [/latex]

Question 8.27: Figure 8.59 (a) shows a preliminary design for a two-stage a...

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