Question 4.4: Objective: Design the bias of a MOSFET circuit such that the...

Objective: Design the bias of a MOSFET circuit such that the Q-point is in the middle of the saturation region. Determine the resulting small-signal voltage gain.

Specifications: The circuit to be designed has the configuration shown in Figure 4.17. Let R1R2=100 kΩR_{1}||R_{2} = 100  kΩ. Design the circuit such that the Q-point is IDQ=2 mAI_{DQ} = 2  mA and the Q-point is in the middle of the saturation region.

Choices: A transistor with nominal parameters VTN=1 V,k´n=80 µA/V2,W/L=25V_{T N} = 1  V, k´_{n} = 80  µA/V^{2} , W/L = 25, and λ=0.015 V1λ = 0.015  V^{−1} is available.

4.17
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(dc design): The load line and the desired Q-point are given in Figure 4.18. If the Q-point is to be in the middle of the saturation region, the current at the transition point must be 4 mA.
The conductivity parameter is
Kn=k´n2WL=(0.0802)(25)=1 mA/V2K_{n} = \frac{k´_{n}}{2} \cdot \frac{W}{L} = \left(\frac{0.080}{2} \right) (25) = 1  mA/V^{2}

We can now calculate VDS(sat)V_{DS} (sat) at the transition point. The subscript t indicates transition point values. To determine VGStV_{GSt} , we use
IDt=4=Kn(VGSt − VTN)2=1(VGSt − 1)2I_{Dt} = 4 = K_{n}(V_{GSt}  −  V_{T N} )^{2} = 1(V_{GSt}  −  1)^{2}
which yields
VGSt=3 VV_{GSt} = 3  V
Therefore
VDSt=VGSt − VTN=3 − 1=2 VV_{DSt} = V_{GSt}  −  V_{T N} = 3  −  1 = 2  V
If the Q-point is in the middle of the saturation region, then VDSQ=7 VV_{DSQ} = 7  V, which would yield a 10 V peak-to-peak symmetrical output voltage. From Figure 4.17, we can write
VDSQ=VDD − IDQRDV_{DSQ} = V_{DD}  −  I_{DQ} R_{D}
or
RD=VDD − VDSQIDQ=12 − 72=2.5 kΩR_{D} = \frac{V_{DD}  −  V_{DSQ}}{I_{DQ}} = \frac{12  −  7}{2} = 2.5  k\Omega
We can determine the required quiescent gate-to-source voltage from the current equation, as follows:
IDQ=2=Kn(VGSQ − VTN)2=(1)(VGSQ − 1)2I_{DQ} = 2 = K_{n}(V_{GSQ}  −  V_{T N} )^{2} = (1)(V_{GSQ}  −  1)^{2}
or
VGSQ=2.41 VV_{GSQ} = 2.41  V
Then
VGSQ=2.41=(R2R1 + R2)(VDD)=(1R1)(R1R2R1 + R2)(VDD)V_{GSQ} = 2.41 = \left(\frac{R_{2}}{R_{1}  +  R_{2}} \right) (V_{DD}) = \left(\frac{1}{R_{1}} \right) \left( \frac{R_{1} R_{2}}{R_{1}  +  R_{2}} \right) (V_{DD})

=RiR1VDD=(100)(12)R1= \frac{R_{i}}{R_{1}} \cdot V_{DD} = \frac{(100)(12)}{R_{1}}
which yields
R1=498 kΩR_{1} = 498  k \Omega and R2=125 kΩR_{2} = 125  k\Omega

(ac analysis): The small-signal transistor parameters are
gm=2KnIDQ=2(1)(2)=2.83 mA/Vg_{m} = 2 \sqrt{K_{n} I_{D Q}} = 2\sqrt{(1)(2)} = 2.83  mA/V
and
ro=1λIDQ=1(0.015)(2)=33.3 kΩr_{o} = \frac{1}{λ I_{D Q}} = \frac{1}{(0.015)(2)} = 33.3  k\Omega
The small-signal equivalent circuit is the same as shown in Figure 4.7. The small-signal voltage gain is
Av=VoVi=gm(roRD)=(2.83)(33.32.5)A_{v} = \frac{V_{o}}{V_{i}} = −g_{m} (r_{o} || R_{D} ) = −(2.83)(33.3||2.5)
or
Av=6.58A_{v} = −6.58
Comment: Establishing the Q-point in the middle of the saturation region allows the maximum symmetrical swing in the output voltage, while keeping the transistor biased in the saturation region

4.18
4.7

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