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## Q. 6.23

Repeat the above example for a common-gate stage containing a gate resistance of $R_G$ and a source resistance of $R_S$.

## Verified Solution

We draw the small-signal circuit as shown in Fig. 6.54. For the computation of zero-value time constants, the main input is set to zero. Thus, the resulting equivalent circuits are identical for $C_S and C_G$ stages, yielding the same time constants and hence the same bandwidth. After all, the circuits in Figs. 6.53(a) and 6.54 are topologically identical and contain the same poles.

Does this result contradict our earlier assertion that the $C_G$ stage is free from the Miller effect? No, it does not. In a $C_G$ stage, we strive to avoid $R_G$, whereas in a $C_S$ stage, $R_G$ represents the preceding circuit’s output resistance and is inevitable.