Question 16.1: The CMOS SR flip-flop in Fig. 16.4 is fabricated in a 0.18-μ...
The CMOS SR flip-flop in Fig. 16.4 is fabricated in a 0.18-μm process for which μnCox = 4 μpCox = 300 μA/V², Vtn = |Vtp| = 0.5 V, and VDD = 1.8 V. The inverters have (W/L)n = 0.27 μm/0.18 μm and (W/L)p = 4(W/L)n. The four NMOS transistors in the set–reset circuit have equal W/L ratios.
(a) Determine the minimum value required for this ratio to ensure that the flip-flop will switch.
(b) Also, determine the minimum width the set pulse must have for the case in which the W/L ratio of each of the four transistors in the set–reset circuit is selected at twice the minimum value found in (a). Assume that the total capacitance between each of the Q and \overline{Q} nodes and ground is 20 fF.
(a) Figure 16.5(a) shows the relevant portion of the circuit for our present purposes. Observe that since the circuit is in the reset state and regeneration has not yet begun, we assume that vQ = 0 and thus Q2 will be conducting. The circuit is in effect a pseudo-NMOS gate, and our task is to select the W/L ratios for Q5 and Q6 so that VOL of this inverter is lower than VDD/2 (the threshold of the Q3, Q4 inverter whose QN and QP are matched). The minimum required W/L for Q5 and Q6 can be found by equating the current supplied by Q5 and Q6 to the current supplied by Q2 at v_{\overline{Q}} = VDD/2. To simplify matters, we assume that the series connection of Q5 and Q6 is equivalent to a single transistor whose W/L is half the W/L of each of Q5 and Q6 [Fig. 16.5(b)]. Now, since at v_{\overline{Q}} = VDD/2 = 0.9 V and |Vt| = 0.5 V, both this equivalent transistor and Q2 will be operating in the triode region, we can write
IDeq = ID2
300 × \frac{1}{2} \left(\frac{W}{L}\right)_{5} \left[(1.8 − 0.5)\left(\frac{1.8}{2}\right) − \frac{1}{2} \left(\frac{1.8}{2}\right)^{2}\right]
= 75 × \frac{1.08}{0.18} \left[(1.8 − 0.5)\left(\frac{1.8}{2}\right) − \frac{1}{2} \left(\frac{1.8}{2}\right)^{2}\right]
which yields
\left(\frac{W}{L}\right)_{5} = \frac{0.54 μm}{0.18 μm}
and thus
\left(\frac{W}{L}\right)_{6} = \frac{0.54 μm}{0.18 μm}
(b) The value calculated for (W/L)5 and (W/L)6 is the absolute minimum needed for switching to occur. To guarantee that the flip-flop will switch, the value selected for (W/L)5 and (W/L)6 is usually somewhat larger than the minimum. Selecting a value twice the minimum,
(W/L)5 = (W/L)6 = 1.08 μm/0.18 μm
The minimum required width of the set pulse is composed of two components: the time for v_{\overline{Q}} in the circuit of Fig. 16.5(a) to fall from VDD to VDD/2, where VDD/2 is the threshold voltage of the inverter formed by Q3 and Q4 in Fig. 16.4, and the time for the output of the Q3 – Q4 inverter to rise from 0 to VDD/2. At the end of the second time interval, the feedback signal will have traveled around the feedback loop, and regeneration can continue without the presence of the set pulse. We will denote the first component tPHL and the second tPLH, and will calculate their values as follows.
To determine tPHL refer to the circuit in Fig. 16.6 and note that the capacitor discharge current iC is the difference between the current of the equivalent transistor Qeq and the current of Q2,
iC = iDeq − iD2
To determine the average discharge current iC, we calculate iDeq and iD2 at t = 0 and t = tPHL. At t = 0, v_{\overline{Q}} = VDD, thus Q2 is off,
iD2(0) = 0
and Qeq is in saturation,
i_{Deq} = \frac{1}{2} × 300 × \frac{1}{2} × \frac{1.08}{0.18} × (1.8 − 0.5)^{2}
= 760.5 μA
Thus,
iC(0) = 760.5 − 0 = 760.5 μA
At t = tPHL, v_{\overline{Q}} = VDD/2, thus both Q2 and Qeq will be in the triode region,
i_{D2} (t_{PHL}) = 75 × \frac{1.08}{0.18} × \left[(1.8 − 0.5)\left(\frac{1.8}{2}\right) − 0.5 \left(\frac{1.8}{2}\right)^{2}\right]
= 344.25 μA
and
i_{Deq} (t_{PHL}) = 300 × \frac{1}{2} × \frac{1.08}{0.18} \left[(1.8 − 0.5)\left(\frac{1.8}{2}\right) − 0.5 \left(\frac{1.8}{2}\right)^{2}\right]
= 688.5 μA
Thus,
iC (tPHL) = 688.5 − 344.25 = 344.25 μA
and the average value of iC over the interval t = 0 to t = tPHL is
i_{C} |_{av} = \frac{i_{C}(0) + i_{C}(t_{PHL})}{2}
= \frac{760.5 + 344.25}{2} = 552.4 μA
We now can calculate tPHL as
t_{PHL} = \frac{C(V_{DD}/2)}{i_{C} |_{av}} = \frac{20 × 10^{−15} × 0.9}{552.4 × 10^{−6}} = 32.6 ps
Next we consider the time tPHL for the output of the Q3 − Q4 inverter, vQ, to rise from 0 to VDD/2. The value of tPLH can be calculated using the propagation-delay formula derived in Chapter 14 (Eq. 14.52),
t_{PLH} = \frac{α_{p}}{k_{p}^{′} (W/L)_{p} V_{DD}} (14.52)
which is also listed in Table 14.2, namely,
t_{PLH} = \frac{α_{p}C}{k_{p}^{′} (W/L)_{p} V_{DD}}
where
α_{p} = 2 / \left[\frac{7}{4} – \frac{3 |V_{tp}|}{V_{DD}} + \left(\frac{|V_{tp}|}{V_{DD}}\right)^{2}\right]
Substituting numerical values we obtain,
α_{p} = \frac{2}{1.75 – \frac{3 × 0.5}{1.8} + \left(\frac{0.5}{1.8}\right)^{2}} = 2.01
and
t_{PLH} = \frac{2.01 × 20 × 10^{−15}}{75 × 10^{−6} × (1.08/0.18) × 1.8} = 49.7 ps
Finally, the minimum required width of the set pulse can be calculated as
Tmin = tPHL + tPLH = 82.3 ps
