The CMOS SR flip-flop in Fig. 16.4 is fabricated in a 0.18-μm process for which μnCox = 4 μpCox = 300 μA/V², Vtn = |Vtp| = 0.5 V, and VDD = 1.8 V. The inverters have (W/L)n = 0.27 μm/0.18 μm and (W/L)p = 4(W/L)n. The four NMOS transistors in the set–reset circuit have equal W/L ratios.(a) Determine

Question

The CMOS SR flip-flop in Fig. 16.4 is fabricated in a 0.18-μm process for which μ_nC_ox = 4 μ_pC_ox = 300 μA/V², V_tn = |V_tp| = 0.5 V, and V_DD = 1.8 V. The inverters have (W/L)_n = 0.27 μm/0.18 μm and (W/L)_p = 4(W/L)_n. The four NMOS transistors in the set–reset circuit have equal W/L ratios.

(a) Determine the minimum value required for this ratio to ensure that the flip-flop will switch.
(b) Also, determine the minimum width the set pulse must have for the case in which the W/L ratio of each of the four transistors in the set–reset circuit is selected at twice the minimum value found in (a). Assume that the total capacitance between each of the Q and [latex]\overline{Q}[/latex] nodes and ground is 20 fF.

Accepted Answer

(a) Figure 16.5(a) shows the relevant portion of the circuit for our present purposes. Observe that since the circuit is in the reset state and regeneration has not yet begun, we assume that v_Q = 0 and thus Q₂ will be conducting. The circuit is in effect a pseudo-NMOS gate, and our task is to select the W/L ratios for Q₅ and Q₆ so that V_OL of this inverter is lower than V_DD/2 (the threshold of the Q₃, Q₄ inverter whose Q_N and Q_P are matched). The minimum required W/L for Q₅ and Q₆ can be found by equating the current supplied by Q₅ and Q₆ to the current supplied by Q₂ at [latex]v_{\overline{Q}}[/latex] = V_DD/2. To simplify matters, we assume that the series connection of Q₅ and Q₆ is equivalent to a single transistor whose W/L is half the W/L of each of Q₅ and Q₆ [Fig. 16.5(b)]. Now, since at [latex]v_{\overline{Q}}[/latex] = V_DD/2 = 0.9 V and |V_t| = 0.5 V, both this equivalent transistor and Q₂ will be operating in the triode region, we can write

I_Deq = I_D2

[latex]300 × \frac{1}{2} \left(\frac{W}{L}\right)_{5} \left[(1.8 − 0.5)\left(\frac{1.8}{2}\right) − \frac{1}{2} \left(\frac{1.8}{2}\right)^{2}\right][/latex]

[latex]= 75 × \frac{1.08}{0.18} \left[(1.8 − 0.5)\left(\frac{1.8}{2}\right) − \frac{1}{2} \left(\frac{1.8}{2}\right)^{2}\right][/latex]

which yields

[latex]\left(\frac{W}{L}\right)_{5} = \frac{0.54 μm}{0.18 μm}[/latex]

and thus

[latex]\left(\frac{W}{L}\right)_{6} = \frac{0.54 μm}{0.18 μm}[/latex]

(b) The value calculated for (W/L)₅ and (W/L)₆ is the absolute minimum needed for switching to occur. To guarantee that the flip-flop will switch, the value selected for (W/L)₅ and (W/L)₆ is usually somewhat larger than the minimum. Selecting a value twice the minimum,

(W/L)₅ = (W/L)₆ = 1.08 μm/0.18 μm

The minimum required width of the set pulse is composed of two components: the time for [latex]v_{\overline{Q}}[/latex] in the circuit of Fig. 16.5(a) to fall from V_DD to V_DD/2, where V_DD/2 is the threshold voltage of the inverter formed by Q₃ and Q₄ in Fig. 16.4, and the time for the output of the Q₃– Q₄ inverter to rise from 0 to V_DD/2. At the end of the second time interval, the feedback signal will have traveled around the feedback loop, and regeneration can continue without the presence of the set pulse. We will denote the first component t_PHL and the second t_PLH, and will calculate their values as follows.

To determine t_PHL refer to the circuit in Fig. 16.6 and note that the capacitor discharge current i_C is the difference between the current of the equivalent transistor Q_eq and the current of Q₂,

i_C = i_Deq − i_D2

To determine the average discharge current i_C, we calculate i_Deq and i_D2 at t = 0 and t = t_PHL. At t = 0, [latex]v_{\overline{Q}}[/latex] = V_DD, thus Q₂ is off,

i_D2(0) = 0

and Q_eq is in saturation,

[latex]i_{Deq} = \frac{1}{2} × 300 × \frac{1}{2} × \frac{1.08}{0.18} × (1.8 − 0.5)^{2}[/latex]

= 760.5 μA

Thus,

i_C(0) = 760.5 − 0 = 760.5 μA

At t = t_PHL, [latex]v_{\overline{Q}}[/latex] = V_DD/2, thus both Q₂ and Q_eq will be in the triode region,

[latex]i_{D2} (t_{PHL}) = 75 × \frac{1.08}{0.18} × \left[(1.8 − 0.5)\left(\frac{1.8}{2}\right) − 0.5 \left(\frac{1.8}{2}\right)^{2}\right][/latex]

= 344.25 μA

and

[latex]i_{Deq} (t_{PHL}) = 300 × \frac{1}{2} × \frac{1.08}{0.18} \left[(1.8 − 0.5)\left(\frac{1.8}{2}\right) − 0.5 \left(\frac{1.8}{2}\right)^{2}\right][/latex]

= 688.5 μA

Thus,

i_C (t_PHL) = 688.5 − 344.25 = 344.25 μA

and the average value of i_C over the interval t = 0 to t = t_PHL is

[latex]i_{C} |_{av} = \frac{i_{C}(0) + i_{C}(t_{PHL})}{2}[/latex]

[latex]= \frac{760.5 + 344.25}{2} = 552.4 μA[/latex]

We now can calculate t_PHL as

[latex]t_{PHL} = \frac{C(V_{DD}/2)}{i_{C} |_{av}} = \frac{20 × 10^{−15} × 0.9}{552.4 × 10^{−6}} = 32.6 ps [/latex]

Next we consider the time t_PHL for the output of the Q₃ − Q₄ inverter, v_Q, to rise from 0 to V_DD/2. The value of t_PLH can be calculated using the propagation-delay formula derived in Chapter 14 (Eq. 14.52),

[latex]t_{PLH} = \frac{α_{p}}{k_{p}^{′} (W/L)_{p} V_{DD}}[/latex] (14.52)

which is also listed in Table 14.2, namely,

[latex]t_{PLH} = \frac{α_{p}C}{k_{p}^{′} (W/L)_{p} V_{DD}}[/latex]

where

[latex]α_{p} = 2 / \left[\frac{7}{4} - \frac{3 |V_{tp}|}{V_{DD}} + \left(\frac{|V_{tp}|}{V_{DD}}\right)^{2}\right][/latex]

Substituting numerical values we obtain,

[latex]α_{p} = \frac{2}{1.75 - \frac{3 × 0.5}{1.8} + \left(\frac{0.5}{1.8}\right)^{2}} = 2.01[/latex]

and

[latex]t_{PLH} = \frac{2.01 × 20 × 10^{−15}}{75 × 10^{−6} × (1.08/0.18) × 1.8} = 49.7 ps[/latex]

Finally, the minimum required width of the set pulse can be calculated as

T_min = t_PHL + t_PLH = 82.3 ps

Question 16.1: The CMOS SR flip-flop in Fig. 16.4 is fabricated in a 0.18-μ...

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